Collecting statistics for persistent memory

1. An integrated circuit, comprising:

a cache device configured to store:

a first mapping between logical addresses and physical addresses of a first memory, the first mapping being a subset of mapping between logical addresses and physical addresses of the first memory stored in a second memory; and

an access count associated with each of the physical addresses of the first mapping; and

a management controller configured to:

maintain access statistics of the first memory based on the access counts stored in the cache device; and

determine the mapping between logical addresses and physical addresses stored in the second memory based on the access statistics and predicted likelihoods of at least some of the logical addresses receiving an access operation,

wherein the access operation includes a write operation, the access statistics include an accumulative write count for at least some of the physical addresses of the first memory, and the management controller is configured to map a first logical address to a first physical address and a second logical address to a second physical address based on the first logical address being determined to have a higher predicted likelihood of receiving a write operation than the second logical address, the first physical address having a lower accumulative write count than the second physical address.

2. The integrated circuit of claim 1 , wherein the management controller is configured to determine that the first logical address has a higher predicted likelihood of receiving a write operation than the second logical address based on the first logical address being at a beginning of a logical address range of a logical region and the second logical address being at an end of the logical address range.

3. The integrated circuit of claim 1 , wherein the cache device comprises a plurality of entries, each entry of the plurality of entries configured to store a logical address and a physical address of the first mapping, and an access count of the physical address; and

wherein the cache device is configured to update the access count of an entry based on receiving a request to access the entry to translate the logical address of the entry.

4. The integrated circuit of claim 3 , wherein the management controller is configured to update the access statistics of a physical address based on the access count of an entry of the cache device that stores the physical address exceeds a threshold.

5. The integrated circuit of claim 4 , wherein the cache device is configured to, after the management controller updates the access statistics of the physical address, reset the access count of the entry that stores the physical address to zero.

6. The integrated circuit of claim 3 , wherein each entry is configured to store one or more eviction parameters;

wherein the cache device is configured to, based on the one or more eviction parameters of the entry, evict an entry of the plurality of entries when the cache device is full and a request to translate a logical address not found in the cache device is received; and

wherein the management controller is configured to update the access statistics of the physical address of the evicted entry.

7. The integrated circuit of claim 6 , wherein the management controller is configured to update the access statistics of the physical address of the evicted entry based on the access count of the evicted entry being non-zero.

8. The integrated circuit of claim 6 , wherein the one or more eviction parameters of an entry includes a flag indicating whether the entry is evictable; and

wherein the cache device is configured to select an entry for eviction based on the flag indicating that the selected entry is evictable.

9. The integrated circuit of claim 6 , wherein the one or more eviction parameters of an entry includes an indication of how recent the entry was accessed in response to the request; and

wherein the cache device is configured to select an entry for eviction based on the indication indicating that the selected entry is the least recently accessed among the plurality of entries.

10. The integrated circuit of claim 6 , wherein the one or more eviction parameters of an entry includes an identifier of a virtual machine; and

wherein the cache device is configured to select an entry for eviction based on the identifier of the virtual machine of the selected entry and at least one of: the virtual machine having been disabled, or a cache management policy for the virtual machine.

11. The integrated circuit of claim 1 , wherein the cache device is configured to fetch an access count of a physical address to a buffer based on at least one of: an entry of the cache device that stores the physical address being evicted, or the access count exceeding a threshold; and

wherein the management controller is configured to obtain the access count from the buffer and to update the access statistics based on the access count obtained from the buffer.

12. The integrated circuit of claim 1 , wherein the first memory includes a storage class memory (SCM) device; and

wherein the physical addresses comprise SCM block numbers.

13. The integrated circuit of claim 1 , wherein the cache device comprises a translation look-side buffer (TLB).

14. The integrated circuit of claim 1 , wherein the access statistics are stored in the first memory.

15. A method comprising:

storing, at a cache device, a first mapping between logical addresses and physical addresses of a first memory and an access count associated with each of the physical addresses of the first mapping, the first mapping being a subset of mapping between logical addresses and physical addresses of the first memory stored in a second memory;

maintaining access statistics of the first memory based on the access counts stored in the cache device; and

determining the mapping between logical addresses and physical addresses stored in the second memory based on the access statistics and predicted likelihoods of at least some of the logical addresses receiving an access operation,

wherein the access operation includes a write operation, the access statistics include an accumulative write count for at least some of the physical addresses of the first memory, and a first logical address is mapped to a first physical address and a second logical address is mapped to a second physical address based on the first logical address being determined to have a higher predicted likelihood of receiving a write operation than the second logical address, the first physical address having a lower accumulative write count than the second physical address.

16. The method of claim 15 , further comprising:

determining that the first logical address has a higher predicted likelihood of receiving a write operation than the second logical address based on the first logical address being at a beginning of a logical address range of a logical region and the second logical address being at an end of the logical address range.

17. The method of claim 15 , further comprising:

fetching, from the cache device, an access count of a physical address to a buffer based on at least one of: an entry of the cache device that stores the physical address being evicted, or the access count exceeding a threshold;

obtaining, from the buffer, the access count; and

updating the access statistics based on the access count obtained from the buffer.

18. The method of claim 15 , wherein the first memory includes a storage class memory (SCM) device; and

wherein the physical addresses comprise SCM block numbers.