IP Library Granted Patent US 11,462,481
Granted Patent B2
US 11,462,481 · App. 16/936,721 · Granted Oct 4, 2022

Fan-out packaging structure and method of making same

Inventors: Ying-Chieh Pan (New Taipei, TW); Hsiang-Hua Lu (New Taipei, TW); Ching-Yu Ni (New Taipei, TW)
Assignee: Kore Semiconductor Co., Ltd.
H01L23/544H01L21/561H01L21/568H01L23/3121H01L23/49811H01L23/49822H01L25/0655H01L2223/54426
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,462,481
App. No.
16/936,721
Granted
Oct 4, 2022
Kind
B2
Abstract

A fan-out packaging structure includes a redistribution layer and a positioning sheet formed on the redistribution layer. The positioning sheet defines at least one opening penetrating opposite sides of the positioning sheet. At least one chip is mounted in the at least one opening. The redistribution layer comprises at least one conductive circuit. The at least one chip is electrically coupled to a corresponding one conductive circuit.

Claims (23)

1. A method for making a fan-out packaging structure, the method comprising:

providing a carrier board, wherein a redistribution layer is provided on one surface of the carrier board, and the redistribution layer comprises at least one conductive circuit;

forming a positioning sheet on the redistribution layer;

defining at least one opening in the positioning sheet, wherein the at least one opening penetrates through opposite sides of the positioning sheet;

mounting a chip in each of the at least one opening, wherein the chip is electrically coupled to a corresponding one of the at least one conductive circuit;

removing the positioning sheet;

forming a protective layer on surfaces of the chip and on side surfaces of the redistribution layer; and

removing the carrier board to obtain the fan-out packaging structure.

2. The method of claim 1 , wherein:

each of the conductive circuits comprises at least one first connection pad located on a surface of the redistribution layer facing away from the carrier board;

the at least one first connection pad is exposed on the surface of the redistribution layer facing away from the carrier board;

the at least one opening is defined at a position of the at least one first connection pad; and

the chip is electrically coupled to the at least one first connection pad.

3. The method of claim 2 , wherein:

each of the conductive circuits comprises at least one second connection pad located on a surface of the redistribution layer facing the carrier board; and

the at least one first connection pad is electrically coupled to the at least one second connection pad.

4. The method of claim 2 , wherein:

a diameter of the opening increases from a surface of the positioning sheet facing the redistribution layer to a surface of the positioning sheet facing away from the redistribution layer;

the diameter of the opening at the surface of the positioning sheet facing the redistribution layer is equal to a width of the first connection pad;

a gap is defined between the chip and an inner wall of the opening; and

the protective layer is filled in the gap.

5. The method of claim 1 , wherein:

the redistribution layer is adhered to the carrier board by a peelable film.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2022
From: SOCLE TECHNOLOGY CORP.
To: KORE SEMICONDUCTOR CO., LTD.
Reel/Frame 059300/0894 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2020
From: PAN, YING-CHIEH; LU, HSIANG-HUA; NI, CHING-YU
To: SOCLE TECHNOLOGY CORP.
Reel/Frame 053291/0868 →
Priority Claims (1)
CN 201911078460.5 · Nov 6, 2019 · national
Continuity (1)
Related Publication 20210134732A1 · May 6, 2021