IP Library Granted Patent US 11,251,268
Granted Patent B2
US 11,251,268 · App. 16/937,365 · Granted Feb 15, 2022

Semiconductor device with doped structure

Inventors: Miao-Syuan Fan (Hsinchu, TW); Pei-Wei Lee (Hsinchu, TW); Ching-Hua Lee (Hsinchu, TW); Jung-Wei Lee (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L29/0847H01L21/823412H01L21/823418H01L21/823431H01L27/0886H01L29/1037H01L29/401H01L29/41791H01L29/42356H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 11,251,268
App. No.
16/937,365
Granted
Feb 15, 2022
Kind
B2
Abstract

The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.

Claims (42)

1. A method for forming a semiconductor device, comprising:

depositing a film on a substrate, the film comprising lead (Pb);

performing a thermal anneal process on the deposited film and the substrate to form a doped source/drain (S/D) region, wherein the doped S/D region comprises Pb;

performing a treatment process on the doped S/D region; and

forming a S/D contact on the doped S/D region.

2. The method of claim 1 , wherein depositing comprises a chemical vapor deposition (CVD) process.

3. The method of claim 1 , wherein performing the thermal anneal process comprises heating the film and the substrate to a temperature between about 300° C. and about 800° C.

4. The method of claim 1 , wherein performing the treatment process comprises a wet cleaning process.

5. The method of claim 1 , further comprising:

depositing an other film on the substrate, the other film comprising Pb;

performing an other thermal anneal process on the deposited other film and the substrate to form a doped channel region, wherein the channel region comprises Pb;

performing an other treatment process on the doped channel region; and

forming a gate electrode on the doped channel region.

6. A method, comprising:

depositing a first film on a substrate, the first film comprising lead (Pb);

performing a first thermal anneal process on the first film and the substrate to form a doped source/drain (S/D) region, wherein the doped S/D region comprises Pb;

performing a first treatment process on the doped S/D region;

forming a spacer adjacent to the doped S/D region;

depositing a second film on a substrate and in contact with the spacer, the second film comprising lead (Pb);

performing a second thermal anneal process on the second film and the substrate to form a doped channel region, wherein the doped channel comprises Pb; and

performing a second treatment process on the doped channel region.

7. The method of claim 6 , further comprising forming a S/D region in the substrate.

8. The method of claim 7 , further comprising performing a patterning process and an etching process on the first film such that the first film is formed only on the S/D region.

9. The method of claim 6 , further comprising forming a S/D contact on the doped S/D region.

10. The method of claim 6 , wherein the first and second treatments are performed at first and second temperatures, respectively, and wherein the first and second temperatures are different.

11. The method of claim 10 , wherein the first temperature is greater than the second temperature.

12. The method of claim 6 , further comprising removing the first film.

13. The method of claim 6 , further comprising removing the second film.

14. The method of claim 6 , wherein the first treatment process comprises a wet cleaning process.

15. The method of claim 6 , wherein the second treatment process comprises a dry plasma etching process.

16. The method of claim 6 , wherein the first and second treatments are performed at first and second temperatures, respectively, and wherein the first and second temperatures are different.

17. A method, comprising:

forming a source region and a drain region on a substrate;

depositing a first film on a substrate, the first film comprising lead (Pb);

patterning the first film to form first and second portions of the first film on the source region and the drain region, respectively;

performing a first thermal anneal process on the first and second portions of the first film to form a doped source region and a doped drain region, wherein the doped source region and the doped drain region comprise Pb;

forming first and second spacers adjacent to the doped source region and the doped drain region, respectively;

depositing a second film on the substrate and between the first and second spacers, the second film comprising lead (Pb); and

performing a second thermal anneal process on the second film to form a doped channel region between the doped source region and the doped drain region, wherein the doped channel region comprises Pb.

18. The method of claim 17 , further comprising performing a treatment process on the doped source region and the doped drain region.

19. The method of claim 17 , further comprising performing a treatment process on the doped channel region.

20. The method of claim 17 , further comprising removing the first and second films.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2020
From: FAN, MIAO-SYUAN; LEE, PEI-WEI; LEE, CHING-HUA; LEE, JUNG-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 053527/0134 →
Continuity (2)
Provisional Application 62966866 · Jan 28, 2020
Related Publication 20210234000A1 · Jul 29, 2021
Cited By (1)
US 12,288,809