Three-dimensional processor for parallel computing
View Patent ↗A three-dimensional processor (3D-processor) for parallel computing includes a plurality of computing elements. Each computing element comprises at least a three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Deficiency in latency is offset by a large scale of parallelism.
1. A three-dimensional processor (3D-processor) for parallel computing, comprising a single-crystalline semiconductor substrate and a plurality of computing elements including first and second computing elements disposed thereon, each of said computing elements comprising:
at least a three-dimensional memory (3D-M) array including a plurality of vertically stacked memory cells for storing at least a portion of a look-up table (LUT) for a mathematical function, wherein said memory cells are neither in contact with nor interposed by any semiconductor substrate including said single-crystalline semiconductor substrate; and, said memory cells do not comprise any single-crystalline semiconductor material;
an arithmetic logic circuit (ALC) disposed on said single-crystalline semiconductor substrate, wherein said ALC performs at least one arithmetic operation on selected data from said LUT; and, transistors in said ALC comprise at least a single-crystalline semiconductor material;
a plurality of inter-storage-processor (ISP) connections entirely disposed between said 3D-M array and said single-crystalline semiconductor substrate for communicatively coupling said memory cells and said single-crystalline semiconductor substrate, wherein said ISP-connections do not penetrate through any semiconductor substrate including said single-crystalline semiconductor substrate;
wherein said first and second computing elements calculate the values of respective mathematical function in parallel.
2. The processor according to claim 1 , wherein said memory cells comprise at least a poly-crystalline or amorphous semiconductor material.
3. The processor according to claim 1 , wherein said LUT includes functional values or derivative values of said mathematical function.
4. The processor according to claim 1 , wherein said mathematical function includes more operations than arithmetic operations performable by said ALC.
5. The processor according to claim 1 , wherein said mathematical function represents a mathematical model.
6. The processor according to claim 5 , wherein said LUT includes raw measurement data or smoothed measurement data.
7. The processor according to claim 1 , wherein said ALC comprises at least an adder, a multiplier, a multiply-accumulator (MAC), a pre-processing circuit, or a post-processing circuit.
8. The processor according to claim 1 , wherein said ISP-connections comprise a plurality of contact vias.
9. The processor according to claim 1 , wherein said 3D-M array and said ALC at least partially overlap.
10. The processor according to claim 1 , wherein said 3D-M array is a horizontal 3D-M (3D-M H ) array.
11. The processor according to claim 1 , wherein said 3D-M array is a vertical 3D-M (3D-M V ) array.
12. A three-dimensional processor (3D-processor) for parallel computing, comprising a single-crystalline semiconductor substrate and a plurality of computing elements including first and second computing elements disposed thereon, each of said computing elements comprising:
at least a three-dimensional vertical memory (3D-M V ) array including a plurality of vertically stacked memory cells for storing at least a portion of a look-up table (LUT) for a mathematical function, wherein said memory cells are neither in contact with nor interposed by any semiconductor substrate including said single-crystalline semiconductor substrate; and, said memory cells do not comprise any single-crystalline semiconductor material;
an arithmetic logic circuit (ALC) disposed on said single-crystalline semiconductor substrate, wherein said ALC performs at least one arithmetic operation on selected data from said LUT; and, transistors in said ALC comprise at least a single-crystalline semiconductor material;
a plurality of inter-storage-processor (ISP) connections entirely disposed between said 3D-M V array and said single-crystalline semiconductor substrate for communicatively coupling said memory cells and said single-crystalline semiconductor substrate, wherein said ISP-connections do not penetrate through any semiconductor substrate including said single-crystalline semiconductor substrate;
wherein said first and second computing elements calculate the values of respective mathematical function in parallel.
13. The processor according to claim 12 , wherein said memory cells comprise at least a poly-crystalline or amorphous semiconductor material.
14. The processor according to claim 12 , wherein said LUT includes functional values or derivative values of said mathematical function.
15. The processor according to claim 12 , wherein said mathematical function includes more operations than arithmetic operations performable by said ALC.
16. The processor according to claim 12 , wherein said mathematical function represents a mathematical model.
17. The processor according to claim 16 , wherein said LUT includes raw measurement data or smoothed measurement data.
18. The processor according to claim 12 , wherein said ALC comprises at least an adder, a multiplier, a multiply-accumulator (MAC), a pre-processing circuit, or a post-processing circuit.
19. The processor according to claim 12 , wherein said ISP-connections comprise a plurality of contact vias.
20. The processor according to claim 12 , wherein said 3D-M array and said ALC at least partially overlap.