Multiple threshold voltage implementation through lanthanum incorporation
A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.
1. A method comprising:
forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively;
depositing a first blanket lanthanum-containing layer overlapping the first gate dielectric, the second gate dielectric, and the third gate dielectric;
patterning the first blanket lanthanum-containing layer to reveal the second gate dielectric, wherein the first blanket lanthanum-containing layer comprises a remaining portion overlapping the first gate dielectric;
depositing a second blanket lanthanum-containing layer, wherein a first portion of the second blanket lanthanum-containing layer and the remaining portion of the first blanket lanthanum-containing layer overlap the first gate dielectric, and in combination form a first lanthanum-containing layer, and wherein a portion of the second blanket lanthanum-containing layer overlapping and contacting the second gate dielectric forms a second lanthanum-containing layer; and
performing an anneal process to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively, wherein during the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.
2. The method of claim 1 , wherein the first gate dielectric, the second gate dielectric, and the third gate dielectric comprise high-k dielectric layers extending on sidewalls and top surfaces of neighboring gate spacers.
3. The method of claim 1 , wherein when the anneal process is performed, the third gate dielectric is free from any lanthanum-containing layer thereon.
4. The method of claim 1 further comprising, before the anneal process, removing both of the first blanket lanthanum-containing layer and the second blanket lanthanum-containing layer from a second region overlying the third gate dielectric.
5. The method of claim 4 , wherein the first blanket lanthanum-containing layer and the second blanket lanthanum-containing layer are removed from the second region using a same etching mask.
6. The method of claim 1 , wherein the first gate dielectric comprises a silicon oxide layer and a high-k dielectric layer over the silicon oxide layer, and the lanthanum is driven to an interface between the silicon oxide layer and the high-k dielectric layer.
7. The method of claim 1 further comprising:
after the anneal process, removing the first lanthanum-containing layer and the second lanthanum-containing layer.
8. The method of claim 1 , wherein the depositing the first lanthanum-containing layer comprises depositing a lanthanum oxide layer.
9. A method comprising:
forming a first transistor comprising:
forming a first high-k dielectric over a first semiconductor region, wherein the first high-k dielectric comprises a first high-k dielectric material and lanthanum with a first lanthanum atomic percentage; and
forming a first work-function layer over the first high-k dielectric; and
forming a second transistor comprising:
forming a second high-k dielectric over a second semiconductor region, wherein the second high-k dielectric comprises the first high-k dielectric material and lanthanum with a second lanthanum atomic percentage, and wherein the second lanthanum atomic percentage is lower than the first lanthanum atomic percentage; and
forming a second work-function layer over the second high-k dielectric.
10. The method of claim 9 , wherein the forming the first high-k dielectric and the forming the second high-k dielectric comprise:
forming a first lanthanum-containing layer over the first high-k dielectric;
forming a second lanthanum-containing layer over the second high-k dielectric; and
performing an anneal process, wherein the lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer are simultaneously driven into the first high-k dielectric and the second high-k dielectric, respectively.
11. The method of claim 10 , wherein the first lanthanum-containing layer and the second lanthanum-containing layer have different thicknesses.
12. The method of claim 10 , wherein the forming the first lanthanum-containing layer comprises two deposition processes, and an entirety of the second lanthanum-containing layer is deposited by a single deposition process.
13. The method of claim 10 , wherein the forming the first lanthanum-containing layer and the forming the second lanthanum-containing layer comprise:
depositing a first blanket lanthanum-containing layer;
removing a first portion of the first blanket lanthanum-containing layer from the second high-k dielectric, and a second portion of the first blanket lanthanum-containing layer is left on the first high-k dielectric; and
depositing a second blanket lanthanum-containing layer over the second portion of the first blanket lanthanum-containing layer and the second high-k dielectric.
14. The method of claim 10 further comprising, after the anneal process, removing both of the first lanthanum-containing layer and the second lanthanum-containing layer.
15. The method of claim 9 , wherein a ratio of the first lanthanum atomic percentage to the second lanthanum atomic percentage is greater than about 1.3.
16. The method of claim 9 further comprising forming a third transistor comprising:
forming a third high-k dielectric over a third semiconductor region, wherein the third high-k dielectric comprises the first high-k dielectric material, and is free from lanthanum; and
a third work-function layer over the third high-k dielectric, wherein the first work-function layer and the third work-function layer are formed of same materials.
17. A method comprising:
forming a first gate dielectric and a second gate dielectric on a first semiconductor fin and a second semiconductor fin, respectively;
depositing a first lanthanum-containing layer on both of the first gate dielectric and the second gate dielectric;
etching the first lanthanum-containing layer, wherein after the etching, a first portion of the first lanthanum-containing layer is left over the first gate dielectric, and a second portion of the first lanthanum-containing layer over the second gate dielectric is removed;
depositing a second lanthanum-containing layer overlapping both of the first gate dielectric and the second gate dielectric; and
performing an anneal process to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric.
18. The method of claim 17 , wherein the second lanthanum-containing layer is thinner than the first lanthanum-containing layer.
19. The method of claim 17 , wherein after the anneal process, a first lanthanum atomic percentage in the first gate dielectric is equal to about twice a second lanthanum atomic percentage in the second gate dielectric.
20. The method of claim 17 , wherein the first gate dielectric and the second gate dielectric are comprised in a first transistor and a second transistor, respectively, and wherein the first transistor and the second transistor are of opposite conductivity types.