Packages formed using RDL-last process
A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.
1. A structure comprising:
a first device die comprising:
a semiconductor substrate;
a first dielectric layer underlying and contacting the semiconductor substrate; and
a first bond pad extending into the first dielectric layer, with a first bottom surface of the first dielectric layer and a second bottom surface of the first dielectric layer being coplanar;
a gap-filling material comprising:
a first portion encircling the first device die and contacting sidewalls of the first device die; and
a second portion covering the first device die;
vias penetrating through the second portion of the gap-filling material to electrically couple to the first device die, wherein sidewalls of the vias are in contact with the second portion of the gap-filling material;
a plurality of dielectric layers over the gap-filling material;
a plurality of metal lines in the plurality of dielectric layers; and
a plurality of vias interconnecting the plurality of metal lines, wherein the plurality of metal lines and the plurality of vias comprise dual damascene structures.
2. The structure of claim 1 , wherein the first device die comprises:
a first conductive pad;
a passivation layer over the first conductive pad;
a second conductive pad over the passivation layer;
a first via extending from a top surface of the second portion of the gap-filling material to contact the first conductive pad; and
a second via extending from the top surface to contact the second conductive pad.
3. The structure of claim 1 , wherein the first device die and the gap-filling material are free from polymers.
4. The structure of claim 1 further comprising:
a second dielectric layer bonding to the first dielectric layer;
a second bond pad extending into the second dielectric layer and bonding to the first bond pad; and
a blank substrate underlying the second dielectric layer and the second bond pad, wherein the blank substrate is free from active devices and passive devices therein.
5. The structure of claim 1 , wherein the first bond pad has a shape of a grid.
6. The structure of claim 1 , wherein one of the dual damascene structures comprises:
a via and a metal line over and continuously connected to the via, wherein the via and the metal line in combination comprises:
a diffusion barrier layer extending into both of the via and the metal line; and
a copper-containing material over the diffusion barrier layer.
7. The structure of claim 1 , wherein the gap-filling material comprises an oxide.
8. A structure comprising:
a substrate;
a first dielectric layer over and contacting the substrate;
a first bond pad extending into the first dielectric layer and the substrate;
a device die comprising:
a conductive pad; and
a passivation layer comprising a portion over the conductive pad;
a dielectric gap-filling material encapsulating the device die, wherein a portion of the dielectric gap-filling material overlaps the device die, and wherein a top surface of the first dielectric layer is further in contact with the dielectric gap-filling material;
a via over and contacting a top surface of the conductive pad, wherein the via comprises a straight and vertical sidewall penetrating through the dielectric gap-filling material and the passivation layer;
a plurality of low-k dielectric layers over the dielectric gap-filling material;
a plurality of metal lines and vias in the plurality of low-k dielectric layers, wherein the plurality of metal lines and vias are electrically connected to the device die, and the plurality of metal lines and vias form damascene structures; and
a plurality of electrical connectors over and electrically coupling to the plurality of metal lines and vias.
9. The structure of claim 8 , wherein the device die further comprises:
a semiconductor substrate;
a second dielectric layer between and bonding to the first dielectric layer the semiconductor substrate; and
a second bond pad extending into the second dielectric layer, wherein the second bond pad is bonded to the first bond pad.
10. The structure of claim 8 , wherein the substrate comprises a semiconductor material.
11. The structure of claim 8 , wherein the dielectric gap-filling material comprises an oxide.
12. The structure of claim 8 , wherein from a top surface of a top dielectric layer in the plurality of low-k dielectric layers to a bottom surface of the device die, there is no polymer.
13. A structure comprising:
an oxide layer;
a first device die and a second device die, both over and bonding to the oxide layer, wherein the first device die comprises a semiconductor substrate;
a dielectric gap-filling material encapsulating the first device die and the second device die therein;
vias penetrating through the dielectric gap-filling material to electrically couple to the first device die and the second device die;
a plurality of dielectric layers over the vias, wherein the dielectric gap-filling material and the plurality of dielectric layers are formed of inorganic dielectric materials;
a plurality of redistribution lines over and electrically coupling to the vias, wherein the redistribution lines comprise dual damascene structures, and wherein the redistribution lines are in the plurality of dielectric layers; and
a plurality of electrical connectors electrically coupling to the plurality of redistribution lines.
14. The structure of claim 13 , wherein the first device die comprises:
a first conductive pad;
a passivation layer over the first conductive pad; and
a second conductive pad over the passivation layer, wherein the vias comprise a first via and a second via, each penetrating through the dielectric gap-filling material, and wherein the first via physically contacts the first conductive pad, and the second via physically contacts the second conductive pad.
15. The structure of claim 14 , wherein the first via comprises a first straight edge extending from a top surface of the dielectric gap-filling material to the first conductive pad, and the second via comprises a second straight edge extending from the top surface of the dielectric gap-filling material to the second conductive pad.
16. The structure of claim 13 further comprising a plurality of low-k dielectric layers, wherein the plurality of redistribution lines are in the plurality of low-k dielectric layers.
17. The structure of claim 13 , wherein the first device die and the second device die are free from polymers.
18. The structure of claim 4 , wherein the blank substrate comprises a micro trench therein.
19. The structure of claim 8 , wherein the substrate comprises a micro trench therein, wherein the micro trench comprises a first end and a second end, and wherein both of the first end and the second end extend to a bottom surface of the substrate.
20. The structure of claim 13 , wherein an entire part of the structure extending from a top surface of a top dielectric layer in the plurality of dielectric layers to a bottom surface of the first device die is free from polymer therein.