Transistors and memory arrays
Some embodiments include integrated memory having an array of access transistors. Each access transistor includes an active region which has a first source/drain region, a second source/drain region and a channel region. The active regions of the access transistors include semiconductor material having elements selected from Groups 13 and 16 of the periodic table. First conductive structures extend along rows of the array and have gating segments adjacent the channel regions of the access transistors. Heterogenous insulative regions are between the gating segments and the channel regions. Second conductive structures extend along columns of the array, and are electrically coupled with the first source/drain regions. Storage-elements are electrically coupled with the second source/drain regions. Some embodiments include a transistor having a semiconductor oxide channel material. A conductive gate material is adjacent to the channel material. A heterogenous insulative region is between the gate material and the channel material.
1. A transistor comprising semiconductor oxide channel material comprising a vertically-extending pillar, conductive gate material extending vertically adjacent only one side of the channel material, and a heterogenous insulative region between the gate material and the channel material.
2. The transistor of claim 1 wherein the heterogeneous insulative region includes an abrupt interface between two different insulative compositions.
3. The transistor of claim 1 wherein the heterogeneous insulative region includes at least three different compositions.
4. The transistor of claim 1 wherein the heterogeneous insulative region includes a second composition sandwiched between a first composition and a third composition; wherein the first composition is directly against the channel material and the third composition is directly against the gate material; and wherein the second composition has a higher dielectric constant than the first and third compositions.
5. The transistor of claim 4 wherein the first composition includes fixed charges.
6. The transistor of claim 4 wherein the first composition joins to the semiconductor oxide material along an interface having interfacial traps; and wherein said interface has a density of the interfacial traps of less than or equal to about 1×10 8 traps/cm 2 .
7. The transistor of claim 4 wherein the first composition is non-ferroelectric.
8. The transistor of claim 4 wherein two or more of the first, second and third compositions are of about the same thickness as one another.
9. The transistor of claim 4 wherein the first composition is discontinuous.
10. The transistor of claim 4 wherein the first composition comprises a thickness within a range of from about 5 Å to about 20 Å.
11. The transistor of claim 4 wherein the second composition comprises a thickness within a range of from about 30 Å to about 100 Å.
12. The transistor of claim 4 wherein the third composition is discontinuous.
13. The transistor of claim 4 wherein the third composition comprises a thickness within a range of from about 5 Å to about 20 Å.
14. The transistor of claim 4 wherein the first composition comprises aluminum and oxygen, the second composition comprises one or more transition metals in combination with oxygen, and the third composition comprises silicon and oxygen.
15. The transistor of claim 14 wherein the second composition comprises niobium in combination with one or more of carbon, oxygen, nitrogen and silicon.
16. The transistor of claim 4 wherein the third composition comprises oxygen in combination with one or more of silicon, nitrogen, carbon and aluminum.
17. The transistor of claim 4 wherein the third composition comprises one or more of doped silicate glass, SiO, AlO, AlSiO, SiOC and SiON, where the chemical formulas indicate primary constituents rather than specific stoichiometries.
18. The transistor of claim 4 wherein the gate material comprises metal, and wherein the third composition alleviates fermi-level pinning between the second composition and the gate material.
19. The transistor of claim 1 wherein the semiconductor oxide includes InGaZnO, where the chemical formula indicates primary constituents rather than a specific stoichiometry.
20. An integrated assembly comprising:
a channel material comprising semiconductor material which includes at least one element selected from the group consisting of gallium, indium and mixtures thereof, in combination with at least one element selected from the group consisting of oxygen, sulfur, selenium, tellurium and mixtures thereof;
a first insulative composition directly adjacent the channel material;
a second insulative composition adjacent the first insulative composition and having a higher dielectric constant than the first insulative composition, the second insulative composition comprising niobium;
a conductive gate material spaced from the first insulative composition by at least the second insulative composition; and
a pair of source/drain regions, the pair of source/drain regions do not comprise the same material as the channel material.
21. The integrated assembly of claim 20 wherein the gate material extends vertically along only one side of the channel material.
22. The integrated assembly of claim 20 wherein the channel material has two ends and a central region between the two ends, and wherein the gate material entirely surrounds a lateral periphery of the central region of the channel material.
23. The integrated assembly of claim 20 wherein the channel material is supported by an underlying semiconductor base; wherein the channel material is elongated along a first direction; and wherein the first direction is substantially orthogonal to a primary surface of the semiconductor base.
24. An integrated assembly comprising:
a channel material comprising semiconductor material which includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table;
a first insulative structure having a region directly adjacent the channel material;
a second insulative structure adjacent the first insulative structure and having a higher dielectric constant than the first insulative structure;
a conductive gate material adjacent the second insulative structure;
wherein the first insulative structure comprises two different layers which join along an abrupt interface;
wherein the second insulative structure comprises at least two different layers which join along an abrupt interface; and
wherein the channel material comprises a vertically-extending pillar and the conductive gate material is adjacent only one side of the channel material.
25. The integrated assembly of claim 24 wherein the second insulative structure comprises only a single homogeneous material.
26. The integrated assembly of claim 24 wherein the second insulative structure comprises two different materials which join along an abrupt interface.
27. Integrated memory comprising:
an array of access transistors; each of the access transistors comprising an active region which includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions; the array comprising rows and columns;
the active regions of the access transistors including semiconductor material which includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table; said semiconductor material being within at least the channel regions and one of the first and second source/drain regions;
first conductive structures extending along the rows of the array and having gating segments extending vertically adjacent only one side of the channel regions of the access transistors;
heterogenous insulative regions between the gating segments and the channel regions;
second conductive structures extending along the columns of the array; the second conductive structures being electrically coupled with the first source/drain regions; and
storage-elements electrically coupled with the second source/drain regions.
28. The integrated memory of claim 27 wherein the semiconductor material is a semiconductor oxide.
29. The integrated memory of claim 27 wherein each of the heterogeneous insulative regions includes a second composition sandwiched between a first composition and a third composition; wherein the first composition is directly against the channel material and the third composition is directly against the gate material; and wherein the second composition has a higher dielectric constant than the first and third compositions.
30. The integrated memory of claim 27 wherein the storage-elements are capacitors.
31. The integrated memory of claim 27 wherein the first conductive structures are coupled with driver circuitry.
32. The integrated memory of claim 31 wherein the second conductive structures are coupled with sensing circuitry.
33. The integrated memory of claim 32 wherein at least some of the driver circuitry and/or at least some of the sensing circuitry is directly under the array of the access transistors.
34. The transistor of claim 1 wherein the heterogenous insulative region comprises a first insulative structure having two different materials which join along an abrupt interface.
35. The transistor of claim 1 wherein the semiconductor oxide channel material comprises at least one element selected from the group consisting of sulfur, selenium, tellurium and mixtures thereof.
36. The transistor of claim 1 further comprising a pair of source/drain regions, the pair of source/drain regions do not comprise the semiconductor oxide material of the channel material.
37. The transistor of claim 1 wherein the heterogenous insulative region comprises niobium.
38. The integrated assembly of claim 20 wherein the channel material comprises at least one element selected from the group consisting of sulfur, selenium, tellurium and mixtures thereof.
39. The integrated assembly of claim 20 wherein the channel material comprises a vertically-extending pillar and the conductive gate material is adjacent only one side of the channel material.
40. The integrated assembly of claim 24 wherein the channel material comprises at least one element selected from the group consisting of sulfur, selenium, tellurium and mixtures thereof.
41. The integrated assembly of claim 24 further comprising a pair of source/drain regions, the pair of source/drain regions comprise a different composition than the semiconductor material of the channel material.
42. The integrated assembly of claim 24 wherein the second insulative structure comprises niobium.
43. The integrated memory of claim 27 wherein the channel material comprises at least one element selected from the group consisting of sulfur, selenium, tellurium and mixtures thereof.
44. The integrated memory of claim 27 wherein the insulative regions comprise niobium.
45. The transistor of claim 1 wherein, in a vertical cross section, the gate material extends a same length as the heterogenous insulative region.
46. The transistor of claim 1 wherein, in a horizontal cross section, the gate material extends a greater length than the heterogenous insulative region.
47. The transistor of claim 5 wherein the fixed charge is greater than or equal to about 1×10 12 atoms/cm 3 .
48. The integrated assembly of claim 20 wherein:
the first insulative composition comprises two different layers; and
the second insulative composition comprises at least two different layers.
49. The integrated assembly of claim 20 wherein the second insulative composition comprises at least three different layers.
50. The integrated assembly of claim 24 wherein the second insulative structure comprises at least three different layers.
51. The integrated assembly of claim 50 further comprising a third insulative structure adjacent the second insulative structure.
52. The integrated memory of claim 27 wherein the insulative regions comprise:
a first insulative composition comprising two different layers; and
a second insulative composition comprising at least two different layers.
53. The integrated memory of claim 52 wherein the second insulative composition comprises at least three different layers.
54. An integrated assembly comprising:
a channel material comprising semiconductor material which includes at least one element selected from the group consisting of gallium, indium and mixtures thereof, in combination with at least one element selected from the group consisting of oxygen, sulfur, selenium, tellurium and mixtures thereof;
a first insulative composition directly adjacent the channel material;
a second insulative composition adjacent the first insulative composition and having a higher dielectric constant than the first insulative composition, the second insulative composition comprising niobium;
a conductive gate material spaced from the first insulative composition by at least the second insulative composition; and
wherein the gate material extends vertically along only one side of the channel material.
55. An integrated assembly comprising:
a channel material comprising semiconductor material which includes at least one element selected from the group consisting of gallium, indium and mixtures thereof, in combination with at least one element selected from the group consisting of oxygen, sulfur, selenium, tellurium and mixtures thereof;
a first insulative composition directly adjacent the channel material;
a second insulative composition adjacent the first insulative composition and having a higher dielectric constant than the first insulative composition, the second insulative composition comprising niobium;
a conductive gate material spaced from the first insulative composition by at least the second insulative composition; and
wherein the channel material comprises a vertically-extending pillar and the conductive gate material is adjacent only one side of the channel material.
56. An integrated assembly comprising:
a channel material comprising semiconductor material which includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table;
a first insulative structure having a region directly adjacent the channel material;
a second insulative structure adjacent the first insulative structure and having a higher dielectric constant than the first insulative structure;
a conductive gate material adjacent the second insulative structure;
wherein the first insulative structure comprises two different layers which join along an abrupt interface;
wherein the second insulative structure comprises at least two different layers which join along an abrupt interface; and
a pair of source/drain regions, the pair of source/drain regions comprise a different composition than the semiconductor material of the channel material.