IP Library Granted Patent US 10,978,392
Granted Patent B2
US 10,978,392 · App. 16/941,605 · Granted Apr 13, 2021

Electrical chip and optical module

Inventor: Teruaki Yagoshi (Kawasaki, JP)
Assignee: FUJITSU LIMITED
H01L23/5286G02B6/4246H04B10/40
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Quick Facts
Patent No.
US 10,978,392
App. No.
16/941,605
Granted
Apr 13, 2021
Kind
B2
Abstract

An electrical chip includes a plurality of electrical signal processing circuits arranged side by side on a chip board, the electrical signal processing circuits that processes electrical signals transmitted to each of a plurality of lanes for each lane; and a power supply wiring network provided in an area overlapping with each of the plurality of electrical signal processing circuits and including wires formed into a mesh shape for supplying power to each of the plurality of electrical signal processing circuits, wherein the power supply wiring network includes a slit obtained by separating a part of the wires in each area corresponding to a boundary between the lanes.

Claims (26)

1. An electrical chip comprising:

a plurality of electrical signal processing circuits arranged side by side on a chip board, the electrical signal processing circuits that processes electrical signals transmitted to each of a plurality of lanes for each lane; and

a power supply wiring network provided in an area overlapping with each of the plurality of electrical signal processing circuits and including wires formed into a mesh shape for supplying power to each of the plurality of electrical signal processing circuits,

wherein the power supply wiring network includes a slit obtained by separating a part of the wires in each area corresponding to a boundary between the lanes.

2. The electrical chip according to claim 1 ,

wherein the power supply wiring network includes:

a plurality of first wires parallel to each other provided in a first wiring layer and extending in a direction in which the plurality of electrical signal processing circuits is arranged; and

a plurality of second wires parallel to each other provided in a second wiring layer stacked on the first wiring layer and extending in a direction orthogonal to the direction in which the plurality of electrical signal processing circuits is arranged, and

wherein the slit is formed of a portion in which a part of the plurality of first wires is separated.

3. The electrical chip according to claim 2 ,

wherein either a power supply potential or a ground potential is applied to the first wires and the second wires, and

out of the first wires and the second wires, wires to which the same potential is applied are connected to each other via a via at an intersection of the wires.

4. The electrical chip according to claim 1 ,

wherein the slit is arranged in an area corresponding to a portion in which a power consumption amount is relatively large in the electrical signal processing circuit.

5. An optical module comprising:

an electrical chip that processes an electrical signal; and

an optical chip that processes an optical signal corresponding to the electrical signal,

wherein the electrical chip includes:

a plurality of electrical signal processing circuits arranged side by side on a chip board, the electrical signal processing circuits that processes electrical signals transmitted to each of a plurality of lanes for each lane; and

a power supply wiring network provided in an area overlapping with each of the plurality of electrical signal processing circuits and including wires formed into a mesh shape for supplying power to each of the plurality of electrical signal processing circuits, and

wherein the power supply wiring network includes a slit obtained by separating a part of the wires in each area corresponding to a boundary between the lanes.

6. The optical module according to claim 5 , further comprising:

a module board including an opening,

wherein the optical chip is accommodated in the opening,

the electrical chip is connected to the module board in a state of protruding to the opening, and

a portion of the electrical chip protruding to the opening is connected to the optical chip.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2025
From: FUJITSU LIMITED
To: 1FINITY INC.
Reel/Frame 072432/0779 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2020
From: YAGOSHI, TERUAKI
To: FUJITSU LIMITED
Reel/Frame 053348/0970 →
Priority Claims (1)
JP JP2019-158660 · Aug 30, 2019 · national
Continuity (1)
Related Publication 20210066195A1 · Mar 4, 2021
Cited By (1)
US 12,199,051