Methods and system for an integrated circuit

1. An integrated circuit, comprising:

a first input terminal adapted to receive an input data signal;

a second input terminal adapted to receive a clock signal;

a counter circuit adapted to generate a count value according to an oscillator;

an interface circuit connected to the first and second input terminals, and configured to generate a write protect signal according to the count value; and

a register in communication with the interface circuit and adapted to:

store an address; and

receive the write protect signal, wherein the write protect signal prevents changes to the address.

2. The integrated circuit according to claim 1 , wherein the interface circuit comprises: a compare circuit and a plurality of flip-flop circuits; wherein the compare circuit and the flip-flop circuits are adapted to operate together to generate the write protect signal.

3. The integrated circuit according to claim 2 , wherein the compare circuit is adapted to generate the write protect signal according to the input data signal and the output signal.

4. The integrated circuit according to claim 1 , wherein the interface circuit comprises:

a first flip-flop circuit, from the plurality of flip-flop circuits, connected to the first input terminal and adapted to receive the input data signal; and

a second flip-flop circuit, from the plurality of flip-flop circuits, connected to the second input terminal and adapted to generate an output signal.

5. The integrated circuit according to claim 1 , wherein the write protect signal comprises a high value and a low value.

6. The integrated circuit according to claim 5 , wherein the write protect signal prevents changes to the address when:

the output signal is a high value;

the input data signal is a low value; and

the write protect signal is the high value.

7. The integrated circuit according to claim 1 , further comprising a non-volatile memory in communication with the register.

8. The integrated circuit according to claim 1 , wherein the address of the register comprises one of a default address or a new address.

9. The integrated circuit according to claim 8 , wherein the interface is adapted to change the address of the register from the default address to the new address.

10. A method for assigning addresses to plurality of slave devices connected to a host device, comprising:

transmitting a first communication signal to each slave device using a default address;

receiving a first acknowledgment signal from each slave device;

detecting one of the slave devices as having a first counter value that is the lowest-magnitude counter value relative to first counter values of the remaining slave devices; and

writing a first new address to the slave device associated with the first counter value having the lowest-magnitude counter value.

11. The method according to claim 10 , further comprising:

transmitting a second communication signal to each slave device using the default address;

receiving a second acknowledgment signal from at least two slave devices;

detecting one of the slave devices as having a second counter value that is the lowest-magnitude counter value relative to second counter values of the remaining slave devices; and

writing a second new address to the slave device associated with the second counter having the lowest-magnitude counter value.

12. The method according to claim 10 , further comprising receiving a non-acknowledgment signal from at least one of the slave devices.

13. A system, comprising:

a host device; and

a plurality of integrated circuits connected to the host device via a common bus, wherein each integrated circuit comprises a first input terminal adapted to receive a data signal and a second input terminal adapted to receive a clock signal, and wherein each integrated circuit is configured to:

communicate with the host using a stored address, wherein the stored address is one of a default address or a new address;

generate a count value; and

generate a write protect signal according to the count value;

wherein the host device is adapted to write the new address to one of the integrated circuits based on the generated count value.

14. The system according to claim 13 , wherein each integrated circuit comprises:

a counter circuit adapted to generate the count value according to an oscillator;

an interface circuit connected to the first and second input terminals, and configured to generate a write protect signal according to the count value; and

a register in communication with the interface circuit and adapted to:

store the stored address.

15. The system according to claim 14 , wherein the interface circuit comprises:

a first flip-flop circuit connected to the first input terminal and adapted to receive the data signal; and

a second flip-flop circuit connected to the second input terminal and adapted to generate an output signal.

16. The system according to claim 15 , wherein the interface circuit further comprises a compare circuit connected to the first and second flip-flop circuits, wherein the compare circuit is adapted to generate the write protect signal according to the input signal and the output signal.

17. The system according to claim 16 , wherein the write protect signal prevents changes to the address when:

the output signal is a high value;

the input signal is a low value; and

the write protect signal is the high value.

18. The system according to claim 14 , wherein the write protect signal allows changes to the stored address of one of the integrated circuits and prevents changes to the stored address of the remaining integrated circuits.

19. The system according to claim 13 , wherein the host device is further adapted to:

transmit a first communication signal to each integrated circuit using a default address;

receive a first acknowledgment signal from each integrated circuit;

detect a first lowest-magnitude count value; and

write a first new address to the integrated circuit associated with the lowest-magnitude count value.

20. The system according to claim 19 , wherein the host device is further adapted to:

transmit a second communication signal to each integrated circuit using the default address;

receive a second acknowledgment signal from at least two integrated circuits;

detect a second lowest-magnitude count value; and

write a second new address to the integrated circuit associated with the lowest-magnitude count value.