METHODS AND SYSTEM FOR A RESETTABLE FLIP FLOP
Various embodiments of the present technology may comprise methods and system for a resettable flip flop. The flip flop may receive a clock signal along a first circuit path and a reset signal along a second circuit path. The first circuit path provides a first high voltage value and a first low voltage value, and the second circuit path provides a second high voltage value that is greater than the first high voltage value and a second low voltage value that is less than the first low voltage value.
1 . A system, comprising:
a flip flop circuit comprising a first input terminal and a second input terminal;
a first circuit path connected to the first input terminal and comprising a first type-1 amplifier connected in series with a first level shifter circuit; and
a second circuit path connected to the second input terminal and comprising a second type-1 amplifier connected in series with a second level shifter circuit and a type-2 amplifier.
2 . The system according to claim 1 , wherein the type-1 amplifier comprises a first current path and a second current path in parallel with the first current path; wherein the first current path comprises a first resistor connected in series with a first transistor, and the second current path comprises a second resistor connected in series with a second transistor.
3 . The system according to claim 2 , wherein:
the first and second current paths are configured to connect to a voltage source; and
the type-1 amplifier further comprises a current source connected to the first and second current paths.
4 . The system according to claim 1 , wherein the type-2 amplifier comprises a first current path and a second current path in parallel with the first current path; wherein the first current path comprises a first resistor, a second resistor in series with the first resistor, and a first transistor in series with the second resistor, and the second current path comprises a capacitor in parallel with the first resistor, a third resistor in series with the first resistor, and a second transistor in series with the third resistor.
5 . The system according to claim 4 , wherein the first and second current paths are configured to connect to a voltage source and the type-2 amplifier comprises a current source connected to the first and second current paths.
6 . The system according to claim 1 , wherein the first level shifter circuit is connected to an output terminal of the first type-1 amplifier.
7 . The system according to claim 1 , wherein:
the second level shifter circuit is connected to an output terminal of the second type-1 amplifier; and
the type-2 amplifier is connected to an output terminal of the second level shifter circuit.
8 . The system according to claim 1 , wherein:
the first circuit path generates a clock signal with a first high voltage value and a first low voltage value;
the second circuit path generates a reset signal with a second high voltage value and a second low voltage value;
the second high voltage value is greater than the first high voltage value; and
the second low voltage value is less than the first low voltage value.
9 . The system according to claim 1 , wherein the flip flop circuit further comprises:
a first sub-circuit configured to operate in a track mode and comprising a first transistor that functions as a first current source; and
a second sub-circuit configured to operate in a hold mode and comprising a second transistor that functions as a second current source.
10 . A method for operating a flip flop circuit connected to a first circuit path at a first input terminal and a second circuit path at a second input terminal, comprising:
applying a supply voltage value to the flip flop circuit; and
generating, with the first circuit path, a clock signal having a first high voltage value and a first low voltage value; and
generating, with the second circuit path, a reset signal having a second high voltage value that is greater than the first high voltage value and a second low voltage value that is less than the first low voltage value.
11 . The method according to claim 10 , wherein the first circuit path comprises a first type-1 amplifier and a first level shifter circuit directly connected to an output terminal of the first type-1 amplifier and directly connected to the first input terminal.
12 . The method according to claim 11 , wherein the second circuit path comprises a second type-1 amplifier, a second level shifter circuit connected to an output terminal of the second type-1 amplifier, and a type-2 amplifier directly connected to an output terminal of the second level shifter circuit and directly connected to the second input terminal.
13 . The method according to claim 12 , wherein:
the type-1 amplifier comprises a first current path and a second current path in parallel with the first current path; wherein the first current path comprises a first resistor connected in series with a first transistor, and the second current path comprises a second resistor connected in series with a second transistor; and
the type-2 amplifier comprises a first current path and a second current path in parallel with the first current path; wherein the first current path comprises a first resistor, a second resistor in series with the first resistor, and a first transistor in series with the second resistor, and the second current path comprises a capacitor in parallel with the first resistor, a third resistor in series with the first resistor, and a second transistor in series with the third resistor.
14 . A system, comprising:
a flip flop circuit configured to connect to a voltage source having a supply voltage value and comprising:
a first input terminal and a second input terminal;
a first sub-circuit connected to the first and second input terminals and comprising a first transistor that functions as a first current source and a second transistor having a base-emitter voltage value; and
a second sub-circuit connected to the first and second input terminals and comprising a third transistor that functions as a second current source and a fourth transistor having the base-emitter voltage value; and
a first circuit path connected to the first input terminal, wherein the first circuit path is configured to generate a clock signal having a first high voltage value and a first low voltage value; and
a second circuit path connected to the second input terminal, wherein the second circuit path is configured to generate a reset signal having:
a second high voltage value that is greater than the first high voltage value; and
a second low voltage value that is less than the first low voltage value.
15 . The system according to claim 14 , wherein the first circuit path comprises a first type-1 amplifier and a first level shifter circuit connected to an output terminal of the first type-1 amplifier.
16 . The system according to claim 15 , wherein the type-1 amplifier comprises a first current path and a second current path in parallel with the first current path; wherein the first current path comprises a first resistor connected in series with a first transistor, and the second current path comprises a second resistor connected in series with a second transistor.
17 . The system according to claim 14 , wherein the second circuit path comprises a second type-1 amplifier, a second level shifter circuit connected to an output terminal of the second type-1 amplifier, and a type-2 amplifier connected to an output terminal of the second level shifter circuit.
18 . The system according to claim 17 , wherein the type-2 amplifier comprises a first current path and a second current path in parallel with the first current path; wherein the first current path comprises a first resistor, a second resistor in series with the first resistor, and a first transistor in series with the second resistor, and the second current path comprises a capacitor in parallel with the first resistor, a third resistor in series with the first resistor, and a second transistor in series with the third resistor.
19 . The system according to claim 14 , wherein:
the first high voltage value is equal to a supply voltage value minus the base-emitter voltage value; and
the first low voltage value is equal to the supply voltage value minus the base-emitter voltage value minus a predetermined constant.
20 . The system according to claim 14 , wherein:
the second high voltage value is equal to the first high voltage value plus a predetermined constant; and
the second low voltage value is equal to the first low voltage value minus the predetermined constant.