IP Library Granted Patent US 11,445,140
Granted Patent B2
US 11,445,140 · App. 16/947,604 · Granted Sep 13, 2022

Imaging systems with adjustable amplifier circuitry

Inventors: Rajashekar Benjaram (Bangalore, IN); Gurvinder Singh (Bangalore, IN)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N5/378H01L27/14612H04N5/37457
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Quick Facts
Patent No.
US 11,445,140
App. No.
16/947,604
Granted
Sep 13, 2022
Kind
B2
Abstract

An image sensor may include an array of image pixels. The array of image pixel may be coupled to column readout circuitry. A given image pixel may generate a low light signal and a high light signal for a given exposure. A column line may couple the given image pixel to readout circuitry having amplifier circuitry. The column line may be coupled to an autozeroing transistor for reading out the high light signal and a source follower stage for readout out the low light signal. The amplifier circuitry may receive different common mode voltage depending on whether it is amplifying the low or high light signal. The gain and other operating parameters of the amplifier circuitry may be adjusted based on whether it is amplifying the low or high signal. If desired, separate amplifier circuitry may be implemented for the low and high light signals.

Claims (34)

1. An image sensor comprising:

an image sensor pixel array having an image pixel; and

readout circuitry coupled to the image pixel via a pixel readout path, wherein the readout circuitry comprises:

amplifier circuitry having a first input terminal coupled to the pixel readout path and a second input terminal configured to receive a first voltage during a first mode of operation and a second voltage during a second mode of operation;

a first transistor coupling the pixel readout path to a reference voltage terminal, wherein the first transistor is configured to be activated for the second mode of operation and deactivated for the first mode of operation; and

a second transistor coupling the pixel readout path to a bias transistor configured to generate a bias current.

2. The image sensor defined in claim 1 , wherein the readout circuitry comprises a first switch coupling the second input terminal to a first voltage terminal supplying the first voltage and a second switch coupling the second input terminal to a second voltage terminal supplying the second voltage.

3. The image sensor defined in claim 2 , wherein the readout circuitry includes a sampling switch coupling an output terminal of the amplifier circuitry to sampling circuitry.

4. The image sensor defined in claim 3 , wherein the first input terminal is coupled to the pixel readout path via an input capacitor, and the first input terminal is coupled to the output terminal via an autozero switch along a first path.

5. The image sensor defined in claim 4 , wherein the first input terminal is coupled to the output terminal via a feedback capacitor along a second path.

6. The image sensor defined in claim 5 , wherein the output terminal of the amplifier circuitry is coupled to an additional capacitor via an additional switch.

7. The image sensor defined in claim 1 , wherein the readout circuitry includes a switch configured to selectively provide the first voltage to the second input terminal of the amplifier circuitry, wherein the amplifier circuitry has an output terminal that is coupled to a capacitor via an additional switch, and wherein the switch and the additional switch are controlled based on a same control signal.

8. The image sensor defined in claim 1 , wherein the reference voltage terminal is configured to supply a ground voltage.

9. The image sensor defined in claim 1 , wherein the reference voltage terminal is configured to supply a voltage that is greater than a ground voltage.

10. An image sensor comprising:

image pixels arranged in columns and rows;

column readout circuitry having amplifier circuitry, wherein a given column of image pixels is coupled to the amplifier circuitry via a column line, and the column readout circuitry is configured to read out a low light image signal from a given image pixel in the given column during a first mode of operation and a high light image signal from the given image pixel during a second mode of operation; and

control circuitry configured to control the readout circuitry to provide the amplifier circuitry with a first common mode voltage during the first mode of operation and provide the amplifier circuitry with a second common mode voltage that is greater than the first common mode voltage during the second mode of operation.

11. The image sensor defined in claim 10 , wherein the column readout circuitry includes a first transistor coupling the column line to a reference voltage terminal, and wherein the control circuitry is configured to activate the first transistor during the second mode of operation and deactivate the first transistor during the first mode of operation.

12. The image sensor defined in claim 11 , wherein the column readout circuitry includes a second transistor coupling the column line to a bias transistor, and wherein the control circuitry is configured to activate the second transistor during the first mode of operation and deactivate the second transistor during the second mode of operation.

13. The image sensor defined in claim 10 , wherein the amplifier circuitry includes a non-inverting input terminal coupled to a first voltage terminal supplying the first common mode voltage via a first switch and coupled to a second voltage terminal supplying the second common mode voltage via a second switch.

14. The image sensor defined in claim 13 , wherein the control circuitry is configured to control the readout circuitry to provide the amplifier circuitry with the first common mode voltage by asserting a first control signal received by the first switch and is configured to control the readout circuitry to provide the amplifier circuitry with the second common mode voltage by asserting a second control signal received by the second switch.

15. The image sensor defined in claim 14 , wherein the column readout circuitry includes a third switch coupling an output terminal of the amplifier circuitry to a bandwidth capacitor, and wherein the control circuitry is configured to close the third switch during the first mode of operation and to open the third switch during the second mode of operation.

16. The image sensor defined in claim 15 , wherein the third switch is configured to receive the first control signal.

17. An image sensor comprising:

an image sensor pixel array having an image pixel; and

readout circuitry coupled to the image pixel via a pixel readout path, wherein the readout circuitry comprises:

first amplifier circuitry having a first input terminal coupled to the pixel readout path via a first switch and having a second input terminal configured to receive a first common mode voltage; and

second amplifier circuitry having a first input terminal coupled to the pixel readout path via a second switch and having a second input terminal configured to receive a second common mode voltage greater than the first common mode voltage.

18. The image sensor defined in claim 17 , wherein the readout circuitry comprises:

a first transistor coupling the pixel readout path to a reference voltage terminal; and

a second transistor coupling the pixel readout path to a bias transistor configured to generate a bias current.

19. The image sensor defined in claim 18 , wherein the readout circuitry includes sampling circuitry coupled to an output terminal of the first amplifier circuitry via a third switch and coupled to an output terminal of the second amplifier circuitry via a fourth switch.

20. The image sensor defined in claim 19 , wherein the readout circuitry includes a fifth switch coupling the output terminal of the first amplifier circuitry to a bandwidth capacitor.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 054523, FRAME 0378 Recorded Aug 16, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064615/0602 →
SECURITY INTEREST Recorded Nov 25, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054523/0378 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2020
From: BENJARAM, RAJASHEKAR; SINGH, GURVINDER
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 053442/0869 →
Priority Claims (1)
IN 201911035058 · Aug 30, 2019 · national
Continuity (1)
Related Publication 20210067720A1 · Mar 4, 2021
Cited By (1)
US 12,273,642