PLASMA-SINGULATED, CONTAMINANT-REDUCED SEMICONDUCTOR DIE
Described implementations include a contaminant-free plasma singulation process, in which residues of materials used during plasma singulation are fully removed from sidewalls of a resulting semiconductor die, without damaging the semiconductor die. From such a contaminant-free plasma singulation process, a semiconductor die may be manufactured. The semiconductor die may include a first plurality of sidewall recesses formed in a sidewall of a substrate of the semiconductor die between a first surface and a second surface of the substrate, each having at most a first depth, as well as a second plurality of sidewall recesses formed in the sidewall of the substrate and disposed between the first plurality of sidewall recesses and the second surface, each having at least a second depth that is greater than the first depth.
1 . A semiconductor die, comprising:
a substrate having a first surface and a second surface that is opposed to the first surface;
a first plurality of sidewall recesses formed in a sidewall of the substrate between the first surface and the second surface, each having at most a first depth; and
a second plurality of sidewall recesses formed in the sidewall of the substrate and disposed between the first plurality of sidewall recesses and the second surface, each having at least a second depth that is greater than the first depth.
2 . The semiconductor die of claim 1 , wherein the first plurality of sidewall recesses each have at most a first width, and wherein the second plurality of sidewall recesses each have at least a second width that is greater than the first width.
3 . The semiconductor die of claim 1 , wherein the first plurality of sidewall recesses extends along a first length of the semiconductor die between the first surface and the second surface, and wherein the second plurality of sidewall recesses extends along a second length from the first plurality of sidewall recesses to the second surface.
4 . The semiconductor die of claim 3 , wherein the first length is less than approximately twenty percent of the first length and the second length.
5 . The semiconductor die of claim 1 , wherein the second depth is at least twice the first depth.
6 . The semiconductor die of claim 1 , wherein at least one of the second plurality of sidewall recesses is adjacent to, and has a depth at least twice that of, at least one of the first plurality of sidewall recesses.
7 . A semiconductor die, comprising:
a substrate having a first surface and a second surface that is opposed to the first surface;
a first plurality of sidewall recesses formed in a sidewall of the substrate and extending along a first length of the sidewall from the first surface, the first plurality of sidewall recesses each defining at most a first depth; and
a second plurality of sidewall recesses formed in the sidewall of the substrate and extending along a second length of the sidewall between the first plurality of sidewall recesses and the second surface, the second plurality of sidewall recesses each defining at least a second depth that is greater than the first depth.
8 . The semiconductor die of claim 7 , wherein the first plurality of sidewall recesses each have at most a first width, and wherein the second plurality of sidewall recesses each have at least a second width that is greater than the first width.
9 . The semiconductor die of claim 7 , wherein at least one of the second plurality of sidewall recesses is adjacent to, and has a depth at least twice that of, at least one of the first plurality of sidewall recesses.
10 . A method of making a semiconductor die, comprising:
forming a first plurality of sidewall recesses in a sidewall of a substrate and extending along a first length of the sidewall from a first surface of the substrate, the first plurality of sidewall recesses each defining at most a first depth; and
forming a second plurality of sidewall recesses in the sidewall of the substrate and extending along a second length of the sidewall between the first plurality of sidewall recesses and a second surface of the substrate, the second plurality of sidewall recesses each defining at least a second depth that is greater than the first depth.
11 . The method of claim 10 , wherein forming the first plurality of sidewall recesses comprises performing a first processing cycle with first process parameters, and further wherein forming the second plurality of sidewall recesses comprises performing a second processing cycle with second process parameters.
12 . The method of claim 11 , wherein the first processing cycle and the second processing cycle include a deposition of a passivation layer, an anisotropic etch, and an isotropic etch.
13 . The method of claim 12 , wherein the first process parameters include an isotropic etching time that is less than an isotropic etching time of the second process parameters.
14 . The method of claim 12 , wherein the first process parameters include an isotropic etching flow rate that is less than an isotropic etching flow rate of the second process parameters.
15 . The method of claim 12 , wherein the first process parameters include an isotropic etching power level that is less than an isotropic etching power level of the second process parameters.
16 . The method of claim 12 , further comprising:
rinsing the semiconductor die to remove passivation layer portions from the first plurality of sidewall recesses and from the second plurality of sidewall recesses.
17 . The method of claim 10 , comprising:
forming the first plurality of sidewall recesses each with at most a first width; and
forming the second plurality of sidewall recesses each with at least a second width that is greater than the first width.
18 . An apparatus for singulating a semiconductor die, the apparatus comprising:
a plasma chamber; and
control circuitry configured to singulate a semiconductor wafer disposed within the plasma chamber to obtain the semiconductor die, the control circuitry being configured to cause the apparatus to
form a first plurality of sidewall recesses in a sidewall of a substrate of the semiconductor die and extending along a first length of the sidewall from a first surface of the substrate, the first plurality of sidewall recesses each defining at most a first depth,
form a second plurality of sidewall recesses in the sidewall of the substrate of the semiconductor die and extending along a second length of the sidewall between the first plurality of sidewall recesses and a second surface of the substrate, the second plurality of sidewall recesses each defining at least a second depth that is greater than the first depth, and
detect a process endpoint at which the semiconductor die is singulated with the first plurality of sidewall recesses and the second plurality of sidewall recesses formed in the sidewall.
19 . The apparatus of claim 18 , wherein the control circuitry is configured to cause the apparatus to:
form the first plurality of sidewall recesses including performing a first processing cycle with first process parameters, and
form the second plurality of sidewall recesses including performing a second processing cycle with second process parameters.
20 . The apparatus of claim 18 , wherein the first processing cycle and the second processing cycle include a deposition of a passivation layer, an anisotropic etch, and an isotropic etch.