Semiconductor device having an offset source/drain feature and method of fabricating thereof

1. A semiconductor device, comprising:

a first isolation region and a second isolation region over a substrate;

a first fin structure extending between the first isolation region and the second isolation region;

a first source/drain feature comprising a first epitaxially-grown semiconductor material formed over the first fin structure;

an etch stop layer disposed on sidewalls of the first epitaxially-grown semiconductor material of the first source/drain feature and on an upper surface of the first isolation region; and

wherein the first epitaxially-grown semiconductor material of the first source/drain feature interfaces the upper surface of the first isolation region for a first distance, and first epitaxially-grown semiconductor material of the first source/drain feature interfaces an upper surface of the second isolation region for a second distance, wherein the first distance is different than the second distance.

2. The semiconductor device of claim 1 , wherein the first isolation region and the second isolation region are each a shallow trench isolation (STI) feature and wherein the upper surface of the first isolation region directly interfaces the etch stop layer.

3. The semiconductor device of claim 1 , wherein the second distance is between ¼ and ¾ of the first distance.

4. The semiconductor device of claim 1 , further comprising:

a second fin structure, wherein the first isolation region interposes the second fin structure and the first fin structure; and

a third fin structure, wherein the second isolation region interposes the first fin structure and the third fin structure, wherein the first isolation region extends a first length between the first fin structure and the second fin structure and the second isolation region extends a second length between the first fin structure and the third fin structure.

5. The semiconductor device of claim 4 , wherein the second length is different than the first length.

6. The semiconductor device of claim 4 , wherein a second source/drain feature is formed on the second fin structure, wherein the second source/drain feature interfaces the upper surface of the first isolation region for approximately the first distance.

7. The semiconductor device of claim 1 , wherein a center line of the first source/drain feature is offset from a center line of the first fin structure in a top view.

8. The semiconductor device of claim 1 , wherein the first distance is measured in a first direction and the second distance is measured in a second direction, the second direction parallel and opposite the first direction.

9. The semiconductor device of claim 1 , wherein the first distance extends from the first epitaxially-grown semiconductor material of the first source/drain feature interfacing with the etch stop layer to the first epitaxially-grown semiconductor material of the first source/drain feature interfacing with the first fin structure, and wherein the second distance extends from the first epitaxially-grown semiconductor material of the first source/drain feature interfacing with the etch stop layer to the first epitaxially-grown semiconductor material of the first source/drain feature interfacing with the first fin structure.

10. A semiconductor device, comprising:

a substrate having a first fin structure and a second fin structure, wherein a first isolation feature extends from a first sidewall of the first fin structure to a second sidewall of the second fin structure, and wherein the first isolation feature includes a first surface;

a second isolation feature adjacent a third sidewall of the first fin structure, the third sidewall opposing the first sidewall and a third isolation feature adjacent a fourth sidewall of the second fin structure, wherein the fourth sidewall opposes the second sidewall, and wherein the second isolation feature includes a second surface coplanar the first surface;

a first source/drain feature disposed over the first fin structure and a second source/drain feature disposed over the second fin structure, wherein the first source/drain feature is offset in a first direction from the first fin structure and the second source/drain feature is offset in a second direction from the second fin structure, wherein the first direction is parallel and opposite the second direction, wherein the first source/drain feature has an interface with the second surface of the second isolation feature of a first length and an interface with the first surface of the first isolation feature of a second length, wherein the second length is coplanar to and less than the first length.

11. The semiconductor device of claim 10 , wherein the second source/drain feature has an interface with the first isolation feature of a third length and an interface with the third isolation feature of a fourth length, wherein the third length is coplanar to and less than the fourth length.

12. The semiconductor device of claim 11 , wherein the fourth length is approximately equal to the first length, and the second length is approximately equal to the third length.

13. The semiconductor device of claim 10 , wherein the offset in the first direction includes a centerline of the first source/drain feature shifted toward the first direction from a centerline of the first fin structure, wherein the centerline is an imaginary line extending perpendicular to a top surface of the substrate and defined as a center point of an epitaxial material of the first source/drain feature.

14. The semiconductor device of claim 10 , wherein the offset in the first direction includes a centerline of the first source/drain feature shifted toward the first direction from a centerline of the first fin structure, wherein the centerline is an imaginary line extending parallel to a top surface of the substrate.

15. The semiconductor device of claim 10 , wherein the interface of the first source/drain feature with the second surface of the second isolation feature terminates at first point, the first point being on a sidewall of an etch stop layer interfacing the second surface of the second isolation feature.

16. A semiconductor device, comprising:

a substrate having a first fin structure and a second fin structure, wherein a first isolation feature extends from a first sidewall of the first fin structure to a second sidewall of the second fin structure;

a second isolation feature adjacent a third sidewall of the first fin structure, the third sidewall opposing the first sidewall and a third isolation feature adjacent a fourth sidewall of the second fin structure, wherein the fourth sidewall opposes the second sidewall;

a first epitaxial source/drain feature disposed over the first fin structure and a second epitaxial source/drain feature disposed over the second fin structure, wherein a centerline of the first fin structure is non-collinear with a centerline of the first epitaxial source/drain feature as drawn in a cross-sectional view perpendicular a top surface of the substrate, and a centerline of the first fin structure is non-collinear with a centerline of the first epitaxial source/drain feature as drawn in a top view parallel the top surface of the substrate.

17. The semiconductor device of claim 16 , wherein a centerline of the second fin structure is non-collinear with a centerline of the second epitaxial source/drain feature, wherein the centerline of the second epitaxial source/drain feature is drawn through a centerpoint of a bottommost surface of the second epitaxial source/drain feature interfacing the second fin structure and the second isolation feature.

18. The semiconductor device of claim 17 , wherein the centerline of the first fin structure is disposed a first distance in a first direction from the centerline of the first epitaxial source/drain feature, and the centerline of the second fin structure is disposed a second distance in a second direction from the centerline of the second epitaxial source/drain feature, wherein the first direction and second direction are parallel and opposing one another.

19. The semiconductor device of claim 18 , wherein the semiconductor device further includes a first gate structure associated with the first epitaxial source/drain feature and a second gate structure associated with the second epitaxial source/drain feature, wherein each of the first gate structure and the second gate structure wrap a channel region.

20. The semiconductor device of claim 16 , wherein the first epitaxial source/drain feature and the second epitaxial source/drain feature are silicon germanium.