Method for processing page fault by processor

1. A method for processing a page fault by using a processor and an operating system, the method comprising:

performing demand paging depending on an application operation;

loading, at the processor, data on a memory in response to the demand paging; and

processing the page fault selectively by the operating system or by the processor, dependent on a result of checking bits of a page table entry,

wherein the loading of the data on the memory includes;

looking up, at a memory management unit constituting the processor, a page table;

checking a present bit of the page table entry;

when the present bit corresponds to a first value determined in advance, checking a logical block address (LBA) bit of the page table entry; and

when the LBA bit corresponds to a second value determined in advance, processing the page fault through a fault processing unit constituting the processor.

2. The method of claim 1 , wherein the processing of the page fault includes:

transferring information associated with the page fault to a page miss handler constituting the fault processing unit;

looking up page miss status holding registers (PMSHR) based on the information associated with the page fault;

allocating a page for processing the page fault based on information stored in the PMSHR;

updating, at the page miss handler, the page table entry; and

transferring, at the page miss handler, a page fault processing completion message to a memory management unit.

3. The method of claim 2 , further comprising:

after the allocating of the page for processing the page fault, transferring, at the page miss handler, an I/O request to a host control unit;

processing, at the host control unit, an I/O through a queue register; and

transferring, at the host control unit, an I/O completion message to the page miss handler.

4. The method of claim 3 , further comprising:

snooping, at the host control unit, a head address of a completion queue with regard to the I/O request and checking whether to transfer the I/O completion message to the page miss handler.

5. The method of claim 1 , wherein the page table entry includes information associated with the present bit, information associated with the LBA bit, information associated with a socket identifier (ID), information associated with a device ID, and information associated with a logical block address.

6. The method of claim 1 , further comprising:

when the present bit corresponds to a third value determined in advance, returning a page frame number;

when the LBA bit corresponds to a fourth value determined in advance, calling an operating system page fault handler;

allocating a page from an operating system memory allocator;

inserting the page into a page cache; and

transferring an I/O request through a device driver and updating the page table entry upon I/O completion.

7. The method of claim 1 , further comprising:

calling, at the operating system, a kernel thread periodically;

allocating, at an operating system memory allocator, a page;

performing direct memory access (DMA) mapping of the allocated page; and

refilling a free page by inserting the allocated page into a free page queue.

8. The method of claim 1 , further comprising:

looking up, at the operating system, the page table periodically;

checking, at the operating system, an LBA bit of a page middle directory (PMD) entry and an LBA bit of aa page upper directory (PUD) entry;

checking, at the operating system, the LBA bit and the present bit of the page table entry;

inserting a page corresponding to the page table entry into a cache or a least recently used (LRU) list based on the LBA bit and the present bit; and

updating page-related meta data.

9. A processor for processing a page fault, comprising:

a memory management unit configured to look up a page table and to check a present bit of a page table entry,

wherein, when the present bit corresponds to first value determined in advance, the memory management unit checks a logical block address (LBA) bit of the page table entry; and

a fault processing unit configured to process the page fault when the LBA bit corresponds to a second value determined in advance,

wherein the fault processing unit includes a page miss handler configured to:

receive information associated with the page fault;

look up pane miss status holding registers (PMSHR) based on the information associated with the page fault;

allocate a gage for processing the page fault based on information stored in the PMSHR;

update the page table entry; and

transfer a page fault processing completion message to a memory management unit.

10. The processor of claim 9 , wherein the fault processing unit further includes a host control unit configured to:

receive an I/O request from the page miss handler;

process an I/O through a queue register, and

transfer an I/O completion message to the page miss handler.

11. The processor of claim 10 , wherein the host control unit snoops a head address of a completion queue with regard to the I/O request and checks whether to transfer the I/O completion message to the page miss handler.

12. The processor of claim 9 , wherein the page table entry includes information associated with the present bit, information associated with the LBA bit, information associated with a socket identifier (ID), information associated with a device ID, and information associated with a logical block address.