Semiconductor memory device and method of manufacturing the semiconductor memory device
A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stacked body, an insulating layer overlapping the gate stacked body, a first source layer including a horizontal portion between the gate stacked body and the insulating layer and a protrusion extending from the horizontal portion so as to penetrate the insulating layer, a channel layer penetrating the gate stacked body and extending into the horizontal portion of the first source layer, a first memory pattern between the channel layer and the gate stacked body, and a second source layer disposed between the gate stacked body and the first source layer and coming in contact with the channel layer.
1. A semiconductor memory device, comprising:
a gate stacked body;
an insulating layer overlapping the gate stacked body and including a recessed portion;
a first source layer including a horizontal portion between the gate stacked body and the insulating layer and a protrusion extending from the horizontal portion, wherein an upper surface of the protrusion protrudes toward the insulating layer and a lower surface of the protrusion protrudes toward the insulating layer, wherein at least a portion of the protrusion is disposed in the recessed portion of the insulating layer;
a contact plug directly contacting the protrusion of the first source layer;
a metal source line electrically coupled to the first source layer via the contact plug;
a channel layer penetrating the gate stacked body and extending into the horizontal portion of the first source layer;
a first memory pattern between the channel layer and the gate stacked body; and
a second source layer disposed between the gate stacked body and the first source layer and being in contact with the channel layer;
wherein the first source layer is disposed between the gate stacked body and the contact plug.
2. The semiconductor memory device according to claim 1 , wherein:
the first source layer includes a conductive material, and
the first source layer has a lower resistivity than the second source layer.
3. The semiconductor memory device according to claim 1 , wherein:
the first source layer includes at least one of a tungsten silicide layer and a cobalt silicide layer, and
the second source layer includes a doped semiconductor layer.
4. The semiconductor memory device according to claim 1 , further comprising a second memory pattern disposed between the first source layer and the channel layer.
5. The semiconductor memory device according to claim 1 , wherein the gate stacked body includes alternately stacked interlayer insulating layers and conductive patterns that surround the channel layer.
6. The semiconductor memory device according to claim 5 , wherein the interlayer insulating layers extend so as to be overlapped by a portion of the protrusion of the first source layer.
7. The semiconductor memory device according to claim 1 , wherein:
the first source layer includes a first surface contacting the insulating layer and a second surface opposite the first surface,
the second surface of the first source layer includes a groove defined by the protrusion of the first source layer, and
the groove of the second surface of the first source layer protrudes towards the insulating layer.
8. The semiconductor memory device according to claim 1 , further comprising a core insulating layer penetrating the gate stacked body, wherein:
the channel layer surrounds a sidewall of the core insulating layer, and
the channel layer extends between the core insulating layer and the first source layer so as to close an end portion of the core insulating layer facing the first source layer.
9. The semiconductor memory device according to claim 1 , further comprising:
an upper insulating layer covering the insulating layer and the protrusion;
a contact plug penetrating the upper insulating layer and contacting the protrusion;
a metal source line electrically coupled to the first source layer via the contact plug; and
power lines spaced apart from the metal source line and overlapping the gate stacked body, wherein the insulating layer and the upper insulating layer are interposed between the power lines and the gate stacked body.
10. The semiconductor memory device according to claim 1 , wherein a thickness of the horizontal portion of the first source layer is the same as a thickness of the protrusion of the first source layer.
11. The semiconductor memory device according to claim 1 , wherein the lower surface of the protrusion is located closer to the insulating layer than an upper surface of the horizontal portion.
12. The semiconductor memory device according to claim 1 , wherein the lower surface of the protrusion is located at a same level as an upper surface of the horizontal portion.
13. The semiconductor memory device according to claim 1 , wherein:
the second source layer includes a first portion being in contact with the protrusion and a second portion being in contact with the horizontal portion, and
a thickness of the first portion of the second source layer is greater than a thickness of the second portion of the second source layer.
14. A semiconductor memory device, comprising:
a first gate stacked body surrounding a first channel structure;
a second gate stacked body adjacent to the first gate stacked body and surrounding a second channel structure;
a vertical insulating structure between the first gate stacked body and the second gate stacked body;
a first source layer including:
a protrusion overlapping the vertical insulating structure and having a groove facing the vertical insulating structure;
a first horizontal portion extending from a first side of the protrusion to overlap the first channel structure and the first gate stacked body; and
a second horizontal portion extending from a second side of the protrusion to overlap the second channel structure and the second gate stacked body; and
a second source layer surrounding the first channel structure between the first source layer and the first gate stacked body and surrounding the second channel structure between the first source layer and the second gate stacked body, wherein an upper surface of the protrusion protrudes in a direction away from the vertical insulating structure, and a lower surface of the protrusion protrudes in the direction.
15. The semiconductor memory device according to claim 14 , wherein:
the first source layer includes at least one of a tungsten silicide layer and a cobalt silicide layer, and
the second source layer includes a doped semiconductor layer.
16. The semiconductor memory device according to claim 14 , further comprising:
first memory patterns disposed respectively between the first gate stacked body and the first channel structure and between the second gate stacked body and the second channel structure; and
second memory patterns disposed respectively between the first channel structure and the first source layer and between the second channel structure and the first source layer and spaced apart from the first memory patterns by the second source layer.
17. The semiconductor memory device according to claim 14 , wherein the groove of the protrusion is defined by a curved shape.
18. The semiconductor memory device according to claim 14 , wherein the vertical insulating structure extends into the second source layer.
19. A semiconductor memory device, comprising:
a first gate stacked body surrounding a first channel structure;
a second gate stacked body adjacent to the first gate stacked body and surrounding a second channel structure;
a vertical insulating structure between the first gate stacked body and the second gate stacked body;
a first source layer including:
a protrusion overlapping the vertical insulating structure and having a groove facing the vertical insulating structure;
a first horizontal portion extending from a first side of the protrusion to overlap the first channel structure and the first gate stacked body; and
a second horizontal portion extending from a second side of the protrusion to overlap the second channel structure and the second gate stacked body; and
a second source layer surrounding the first channel structure between the first source layer and the first gate stacked body and surrounding the second channel structure between the first source layer and the second gate stacked body, wherein an upper surface of the protrusion protrudes in a direction away from the vertical insulating structure, and a lower surface of the protrusion protrudes in the same direction,
a contact plug directly contacting the protrusion of the first source layer; and
a metal source line electrically coupled to the first source layer via the contact plug,
wherein the first source layer includes a first surface and a second surface,
wherein the first surface is adjacent to the second source layer and the vertical insulating structure,
wherein the second surface faces an opposite direction to a direction which the first surface faces, the second surface including a first portion corresponding to the protrusion and a second portion corresponding to at least one of the first horizontal portion or the second horizontal portion, and
wherein the first portion of the second surface protrudes compared to the second portion of the second surface.
20. The semiconductor memory device according to claim 14 , wherein:
each of the first gate stacked body and the second gate stacked body includes alternately stacked interlayer insulating layers and conductive patterns, and
each of the first channel structure and the second channel structure includes:
a core insulating layer penetrating the interlayer insulating layers and the conductive patterns; and
a channel layer surrounding a sidewall of the core insulating layer and extending between the core insulating layer and the first source layer so as to close an end portion of the core insulating layer facing the first source layer.