IP Library Granted Patent US 11,558,955
Granted Patent B2
US 11,558,955 · App. 16/950,610 · Granted Jan 17, 2023

Ground discontinuities for thermal isolation

Inventors: Trevor Timpane (Rochester, MN); Layne A. Berge (Rochester, MN); Patryk Gumann (Tarrytown, NY); Sean Hart (Tarrytown, NY); Curtis Eugene Larsen (Eden Valley, MN); Michael Good (Fountain, MN)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H05K1/0201G06N10/00H01L39/04H05K1/0225H05K1/09H05K1/18H05K3/02H05K3/32H05K1/023H05K1/115H05K2201/062H05K2201/10363
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,558,955
App. No.
16/950,610
Granted
Jan 17, 2023
Kind
B2
Abstract

A quantum mechanical circuit includes a substrate; a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor to electrically connect the first electrical conductor and the second electrical conductor. The third electrical conductor is a poor thermal conductor.

Claims (33)

1. A quantum mechanical circuit comprising:

a substrate;

a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and

a third electrical conductor to electrically connect the first electrical conductor and the second electrical conductor,

wherein the third electrical conductor is a poor thermal conductor, wherein the first electrical conductor and the second electrical conductor are electrically decoupled by providing the gap between the first electrical conductor and the second electrical conductor within the substrate.

2. The quantum mechanical circuit according to claim 1 , wherein the third electrical conductor comprises at least one of Copper-Nickel (CuNi) or stainless steel.

3. The quantum mechanical circuit according to claim 2 , wherein CuNi has an electrical resistivity that is approximately 3.8×10-8Qm at ambient temperature and a thermal conductivity that is between about 25 W/m° K and 40 W/m0K.

4. The quantum mechanical circuit according to claim 1 , wherein the first and second electrical conductors comprise copper (Cu).

5. The quantum mechanical circuit according to claim 1 , wherein the first, second and third electrical conductor are configured to transmit a radiofrequency electrical current.

6. The quantum mechanical circuit of claim 1 , wherein the third electrical conductor is coupled to the substrate using fasteners.

7. The quantum mechanical circuit according to claim 1 , wherein the first and second electrical conductors are connected to electrical ground.

8. The quantum mechanical circuit according to claim 1 , further comprising attenuator chips electrically coupled the first and second electrical conductors.

9. The quantum mechanical circuit according to claim 6 , wherein the fasteners comprise brass.

10. A superconducting quantum mechanical computer comprising:

a refrigeration system comprising a temperature-controlled vessel;

a quantum processor disposed within the temperature-controlled vessel, the quantum processor comprising a plurality of qubits; and

a superconducting circuit disposed inside the temperature-controlled vessel, the superconducting circuit comprising:

a substrate;

a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and

a third electric conductor to electrically connect the first electrical conductor and the second electrical conductor, the third electrical conductor being a poor thermal conductor,

wherein each of the plurality of qubits is provided on the substrate and is at least electrically connected to ground via at least one of the first or second electrical conductors, wherein the first electrical conductor and the second electrical conductor are electrically decoupled by providing the gap between the first electrical conductor and the second electrical conductor within the substrate.

11. The superconducting quantum mechanical computer according to claim 10 , wherein the third electrical conductor comprises at least one of Copper-Nickel (CuNi) or stainless steel.

12. The superconducting quantum mechanical computer according to claim 11 , wherein CuNi has an electrical resistivity that is approximately 3.8×10-8 Qm at ambient temperature and a thermal conductivity that is between about 25 W/m° K and 40 W/m0K.

13. The superconducting quantum mechanical computer according to claim 10 , wherein the first and second electric conductors comprise copper (Cu).

14. The superconducting quantum mechanical computer according to claim 10 , wherein the first, second and third electrical conductor are configured to transmit a radiofrequency electrical current.

15. The superconducting quantum mechanical computer according to claim 10 , wherein the third electrical conductor is coupled to the substrate using fasteners.

16. The superconducting quantum mechanical computer according to claim 10 , wherein the first and second electrical conductors are connected to electrical ground.

17. The superconducting quantum mechanical computer according to claim 10 , further comprising attenuator chips electrically coupled to the first and second electrical conductors.

18. A method of manufacturing a quantum mechanical circuit comprising:

providing a substrate having a top face and a bottom face;

forming a conductive layer on at least one of the top face and bottom face of the substrate;

forming conductor lines in a selected pattern on the substrate by removing portions of the conductive layer, the conductor lines including a first electrical conductor and a second electrical conductor on the substrate, the first electrical conductor and the second electrical conductor being spaced apart and separated by a gap therebetween; and

electrically connecting the first electrical conductor and the second electrical conductor using a third electrical conductor, the third electrical conductor being a poor thermal conductor, wherein the first electrical conductor and the second electrical conductor are electrically decoupled by providing the gap between the first electrical conductor and the second electrical conductor within the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2020
From: TIMPANE, TREVOR; BERGE, LAYNE A.; GUMANN, PATRYK; HART, SEAN; LARSEN, CURTIS EUGENE; GOOD, MICHAEL
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 054395/0217 →
Continuity (1)
Related Publication 20220159822A1 · May 19, 2022