Semiconductor device

1. A semiconductor device comprising:

a semiconductor substrate;

a first-conductivity-type drift region provided in the semiconductor substrate;

a gate trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate;

a mesa portion provided in contact with the gate trench portion in an array direction orthogonal to the extending direction;

one or more first-conductivity-type accumulation regions provided in the mesa portion above the drift region and in contact with the gate trench portion, and having a higher doping concentration than the drift region;

a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the gate trench portion; and

a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the gate trench portion and being thinner than the base region in a depth direction of the semiconductor substrate, and provided in at least a part of the mesa portion in the array direction, wherein

the floating region has a higher doping concentration than the one or more accumulation regions.

2. The semiconductor device according to claim 1 , further comprising:

a trench portion in contact with the mesa portion such that the mesa portion is between the trench portion and the gate trench portion,

wherein the floating region is provided in contact with the trench portion.

3. The semiconductor device according to claim 1 , wherein an upper end of the floating region in the depth direction of the semiconductor substrate is provided at a depth position that is deeper than 80% of a vertical distance of the semiconductor substrate.

4. The semiconductor device according to claim 1 , wherein a width of a bottom portion of the gate trench portion is reduced as a depth of the bottom portion of the gate trench portion increases, and the floating region is provided in contact with at least the reduced region in width of the gate trench portion.

5. The semiconductor device according to claim 1 , wherein a length Wbf is larger than a thickness Wb, the length Wbf being a length from a lower end of the base region to an upper end of the floating region in the depth direction of the semiconductor substrate, and the thickness Wb being a width of the base region in the depth direction of the semiconductor substrate.

6. The semiconductor device according to claim 1 , wherein an upper end of the floating region in the depth direction of the semiconductor substrate is provided at a depth position that is deeper than 70% of a vertical distance of the semiconductor substrate.

7. The semiconductor device according to claim 1 , wherein a thickness of the floating region is between 0.1 μm and 1.0 μm.

8. The semiconductor device according to claim 1 , wherein

the base region is provided in the mesa portion above the one or more accumulation regions, and

a length from a lower portion of the base region to a lowermost end of the one or more accumulation regions in the depth direction of the semiconductor substrate is greater than a thickness of the base region.

9. The semiconductor device according to claim 1 , further comprising:

a trench portion in contact with the mesa portion such that the mesa portion is between the trench portion and the gate trench portion; and

another second-conductivity-type floating region that is provided in the mesa portion below the base region, is in contact with the trench portion, is thinner than the base region in the depth direction of the semiconductor substrate, and is provided in at least a part of the mesa portion in the array direction.

10. The semiconductor device according to claim 1 , wherein the floating region in contact with the gate trench portion is not in direct contact with the other floating region in contact with the trench portion in the array direction.

11. The semiconductor device according to claim 1 , wherein a lower end of the floating region in the depth direction of the semiconductor substrate is provided above a lower end of the gate trench portion in the depth direction of the semiconductor substrate.

12. The semiconductor device according to claim 1 , wherein the doping concentration of the floating region is substantially similar or higher than a doping concentration of the base region.

13. The semiconductor device according to claim 1 , wherein the doping concentration of the floating region is higher than a doping concentration of the base region.

14. The semiconductor device according to claim 1 , wherein the floating region is spaced apart from the accumulation regions in the depth direction of the semiconductor substrate by at least the drift region.

15. The semiconductor device according to claim 1 , wherein at least a part of the floating region in the depth direction of the semiconductor substrate is provided in contact with a bottom portion of the gate trench portion.

16. The semiconductor device according to claim 1 , wherein the floating region is provided continuously from the position in contact with the gate trench portion to a predetermined position in the array direction in the mesa portion.

17. The semiconductor device according to claim 1 , wherein the doping concentration of the floating region is 1×10 18 /cm 3 to 3×10 20 /cm 3 .