Methods and devices to improve switching time by bypassing gate resistor
Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the abovementioned performance improvements are maintained.
1. A switching circuit comprising:
an input terminal;
a series arrangement of a plurality of main FET switches, and
at least one main bypass switch block comprising:
an NMOS FET and a PMOS FET, wherein drain terminals of the NMOS FET and the PMOS FET are connected together and source terminals of the NMOS FET and the PMOS FET are connected together;
a main gate resistor coupled across drain-source of each of the NMOS FET and PMOS FET, the main gate resistor coupling the input terminal to a gate terminal of a corresponding main FET switch of the plurality of main FET switches, and
an NMOS FET gate resistor and a PMOS FET gate resistor, wherein a gate terminal of the NMOS FET is coupled to the input terminal through the NMOS FET gate resistor, and a gate terminal of the PMOS FET is coupled to the input terminal through the PMOS FET gate resistor.
2. The switching circuit of claim 1 configured to receive a control voltage applied at the input terminal, the control voltage being configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa.
3. The switching circuit of claim 2 , wherein the at least one main bypass switch block is configured to be open at least during a portion of a first time interval during which the plurality of the main FET switches are in the OFF or the ON state and to be closed at least during a portion of a second time interval during which the plurality of the main switches are transitioning from the OFF to the ON state and vice versa, thereby bypassing the main gate resistor.
4. A switching circuit comprising:
an input terminal;
a series arrangement of a plurality of main FET switches, and
at least one main bypass switch block comprising:
a series arrangement of a plurality of NMOS FETs;
a series arrangement of a plurality of PMOS FETs;
a series arrangement of a plurality of main gate resistors coupling the input terminal to a gate terminal of a corresponding main FET switch of the plurality of main FET switches;
wherein:
drain and source terminals of the NMOS FETs are coupled with corresponding drain and
source terminals of the PMOS FETs respectively;
main gate resistors of the plurality of main gate resistors are coupled across corresponding drain and source terminals of the plurality of NMOS and PMOS FETs;
each NMOS FET of the plurality of NMOS FETs comprises an NMOS gate resistor;
each PMOS FET of the plurality of PMOS FETs comprises a PMOS gate resistor;
gate terminals of the plurality of NMOS FETs are coupled to the input terminal through corresponding NMOS gate resistors, and
gate terminals of the plurality of PMOS FETs are coupled to the input terminal through corresponding PMOS gate resistors.
5. The switching circuit of claim 4 configured to receive a control voltage applied at the input terminal, the control voltage being configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa.
6. The switching circuit of claim 5 , wherein the at least main bypass switch block is configured to be open at least during a portion of a first time interval during which the plurality of the main FET switches are in the OFF or the ON state and to be closed at least during a portion of a second time interval during which the plurality of the main switches are transitioning from the OFF to the ON state and vice versa, thereby bypassing the plurality of main gate resistors.
7. A switching circuit comprising:
an input terminal;
a series arrangement of a plurality of main FET switches,
a plurality of main gate resistors connected to corresponding gate terminals of the plurality of mains FET switches, the plurality of main gate resistors being tied to one another at a main gate resistors common node;
a common bypass switch block comprising:
an NMOS FET, and a PMOS FET wherein drain terminals of the NMOS FET and the PMOS FET are connected together and source terminals of the NMOS FET and the PMOS FET are connected together;
a common gate resistor coupled across drain-source of each of the NMOS FET and PMOS FET, the main gate resistor coupling the input terminal to the common main gate resistor node, and
an NMOS FET gate resistor and a PMOS FET gate resistor, wherein a gate terminal of the NMOS FET is coupled to the input terminal through the NMOS FET gate resistor, and a gate terminal of the PMOS FET is coupled to the input terminal through the PMOS FET gate resistor.
8. The switching circuit of claim 7 configured to receive a control voltage applied at the input terminal, the control voltage being configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa.
9. The switching circuit of claim 8 , wherein the common bypass switch block is configured to be open at least during a portion of a first time interval during which the plurality of the main FET switches are in the OFF or the ON state and to be closed at least during a portion of a second time interval during which the plurality of the main switches are transitioning from the OFF to the ON state and vice versa, thereby bypassing the common gate resistor.
10. A switching circuit comprising:
an input terminal;
a series arrangement of a plurality of main FET switches,
a plurality of main gate resistors connected to corresponding gate terminals of the plurality of mains FET switches, the plurality of main gate resistors being tied to one another at a main gate resistors common node;
a common bypass switch block comprising:
a series arrangement of a plurality of NMOS FETs having a first NMOS FET and a second NMOS FET, the first NMOS FET being the closest to the input terminal and the second NMOS FET being the closest to the main gate resistors common node;
a series arrangement of a plurality of PMOS FETs having a first PMOS FET and a second PMOS FET, the first PMOS FET being the closest to the input terminal and the second PMOS FET being the closest to the main gate resistors common node;
a series arrangement of a plurality of bypass gate resistors coupling the input terminal to the main gate resistors common node;
wherein:
drain and source terminals of the NMOS FETs are coupled with corresponding drain and source terminals of the PMOS FETs respectively;
the plurality of main gate resistors are coupled across corresponding drain and source terminals of the plurality of NMOS and PMOS FETs;
the drain terminals of the first NMOS and PMOS FET are connected together at the input terminal, and
the source terminals of the first NMOS and PMOS FET are connected together at the main gate resistors common node.
11. The switching circuit of claim 10 configured to receive a control voltage applied at the input terminal, the control voltage being configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa.
12. The switching circuit of claim 11 , wherein the common bypass switch block is configured to be open at least during a portion of a first time interval during which the plurality of the main FET switches are in the OFF or the ON state and to be closed at least during a portion of a second time interval during which the plurality of the main switches are transitioning from the OFF to the ON state and vice versa, thereby bypassing the plurality of common gate resistors.
13. A switching circuit comprising:
a series arrangement of a plurality of main FET switches, and
a plurality of main bypass switch blocks each comprising:
a main NMOS FET, and a main PMOS FET wherein drain terminals of the main NMOS FET and the main PMOS FET are connected together and source terminals of the main NMOS FET and the main PMOS FET are connected together, and
a main gate resistor coupled across drain-source of each of the main NMOS FET and main PMOS FET, the main gate resistor connected to a gate terminal of a corresponding main FET switch of the plurality of main FET switches;
a common bypass switch block comprising:
a common NMOS FET, and a common PMOS FET wherein drain terminals of the common NMOS FET and the common PMOS FET are connected together and source terminals of the common NMOS FET and the common PMOS FET are connected together, and a common gate resistor coupled across drain-source of each of the common NMOS FET and common PMOS FET, the common gate resistor coupling a control driver to the main gate resistor,
wherein the drain terminals or the source terminals of the common NMOS FETs and PMOS FETs are connected directly together at an output of the control driver.