Multi-gate device structure

1. A semiconductor device, comprising:

a first transistor in a first device area of a substrate, the first transistor comprising:

a first source/drain feature and a second source/drain feature,

a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature,

a first gate structure wrapping around each of the first plurality of channel members,

a first source/drain contact disposed over the first source/drain feature,

a silicide feature sandwiched between the first source/drain contact and the first source drain feature, and

a first top gate spacer disposed between the first gate structure and the first source/drain contact; and

a second transistor in a second device area of the substrate, the second transistor comprising:

a third source/drain feature and a fourth source/drain feature,

a second plurality of channel members sandwiched between the third source/drain feature and the fourth source/drain feature,

a second gate structure wrapping around each of the second plurality of channel members,

a second source/drain contact disposed over the third source/drain feature, and

a second top gate spacer disposed between the second gate structure and the second source/drain contact,

 wherein a distance between the second top gate spacer and the second source/drain contact is greater than a distance between the first top gate spacer and the first source/drain contact,

 wherein the first source/drain contact and the second source/drain contact comprise a metal or a metal nitride,

 wherein the silicide feature comprises titanium silicide, cobalt silicide, or nickel silicide.

2. The semiconductor device of claim 1 ,

wherein each of the first plurality of channel members extends along a first direction,

wherein each of the second plurality of channel members extends along a second direction,

wherein the first top gate spacer has a first thickness along the first direction,

wherein the second top gate spacer has a second thickness along the second direction, and

wherein the second thickness is greater than the first thickness.

3. The semiconductor device of claim 1 ,

wherein the first transistor further comprises a first etch stop layer disposed between the first source/drain contact and the first top gate spacer,

wherein the second transistor further comprises a second etch stop layer and a low-k dielectric layer disposed between the second source/drain contact and second top gate spacer.

4. The semiconductor device of claim 1 , wherein the first etch stop layer is in direct contact with the first source/drain contact and the first top gate spacer.

5. The semiconductor device of claim 1 , wherein the second etch stop layer is in direct contact with the second top gate spacer and the low-k dielectric layer.

6. The semiconductor device of claim 1 , wherein a thickness of the first etch stop layer is smaller than a thickness of the second etch stop layer.

7. The semiconductor device of claim 1 ,

wherein the first etch stop layer and the second etch stop layer comprise silicon nitride,

wherein the low-k dielectric layer comprises silicon oxide.

8. The semiconductor device of claim 1 ,

wherein the first device area is a high-density device area,

wherein the second device area is a high-voltage device area.

9. The semiconductor device of claim 1 ,

wherein the first gate structure comprises a first gate length,

wherein the second gate structure comprises a second gate length greater than the first gate length.

10. A semiconductor device, comprising:

a first transistor comprising:

a first source/drain feature and a second source/drain feature,

a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature along a first direction,

a first gate structure wrapping around each of the first plurality of channel members, and

a first plurality of inner spacer features disposed between the first gate structure and the first source/drain feature; and

a second transistor comprising:

a third source/drain feature and a fourth source/drain feature,

a second plurality of channel members sandwiched between the third source/drain feature and the fourth source/drain feature along a second direction,

a second gate structure wrapping around each of the second plurality of channel members, and

a second plurality of inner spacer features disposed between the second gate structure and the third source/drain feature,

wherein each of the first plurality of inner spacer features has a first thickness along the first direction,

wherein each of the second plurality of inner spacer features has a second thickness along the second direction,

wherein the second thickness is greater than the first thickness.

11. The semiconductor device of claim 10 , wherein the first plurality of channel members are interleaved by the first plurality of inner spacer features.

12. The semiconductor device of claim 10 , wherein a width of the first source/drain feature along the first direction is smaller than a width of the third source/drain feature along the second direction.

13. The semiconductor device of claim 10 ,

wherein the first transistor further comprises:

a first source/drain contact over the first source/drain feature, and

a first top spacer disposed along sidewalls of the first gate structure above the first plurality of channel members,

wherein the second transistor further comprises:

a second source/drain contact over the third source/drain feature, and

a second top spacer disposed along sidewalls of the second gate structure above the second plurality of channel members,

wherein a distance between the first source/drain contact and the first top spacer is smaller than a distance between the second source/drain contact and the second top spacer.

14. The semiconductor device of claim 13 ,

wherein the first source/drain contact comprises a third width (W 3 ) along the first direction,

wherein the second source/drain contact comprises a fourth width (W 4 ) along the second direction, and

wherein the fourth width (W 4 ) is greater than the third width (W 3 ).

15. The semiconductor device of claim 14 , wherein a ratio of the fourth width to the third width (W 4 /W 3 ) is between about 1.2 and 3.0.

16. A semiconductor device, comprising:

a high-density transistor comprising:

a first gate structure and a second gate structure defining a first pitch, and

a first source/drain contact disposed between the first gate structure and the second gate structure along a first direction; and

a high-voltage transistor comprising:

a third gate structure and a fourth gate structure defining a second pitch greater than the first pitch, and

a second source/drain contact disposed between the third gate structure and the fourth gate structure along a second direction,

wherein the first source/drain contact is spaced apart from the first gate structure by a first distance,

wherein the second source/drain contact is spaced apart from the third gate structure by a second distance greater than the first distance,

wherein the first source/drain contact is disposed directly on a silicide feature,

wherein the first source/drain contact comprises a metal or a metal nitride and the silicide feature comprises titanium silicide, cobalt silicide, or nickel silicide.

17. The semiconductor device of claim 16 ,

wherein the high-density transistor further comprises a first contact via over the first source/drain contact,

wherein the high-voltage transistor further comprises a second contact via over the second source/drain contact,

wherein a width of the first contact via along the first direction is smaller than a width of the second contact via along the second direction.

18. The semiconductor device of claim 16 , further comprising a substrate,

wherein the high-density transistor further comprises:

a first plurality of channel members stacking along a third direction away from the substrate, and

a first source/drain feature in contact with the first plurality of channel members,

wherein the high-voltage transistor further comprises:

a second plurality of channel members stacking along the third direction, and

a second source/drain feature in contact with the second plurality of channel members, and

wherein the first source/drain feature is higher than a topmost channel member of the first plurality of channel members along the third direction,

wherein the second source/drain feature is substantially flush with a topmost channel member of the second plurality of channel members along the third direction.

19. The semiconductor device of claim 16 ,

wherein the high-density transistor further comprises a first etch stop layer disposed between the first source/drain contact and the first gate structure,

wherein the high-voltage transistor further comprises a second etch stop layer disposed between the second source/drain contact and the third gate structure,

wherein a thickness of the second etch stop layer along the second direction is greater than a thickness of the first etch stop layer along the first direction.

20. The semiconductor device of claim 19 ,

wherein the first etch stop layer is in contact with the first source/drain contact,

wherein the second etch stop layer is spaced apart from the second source/drain contact by an interlayer dielectric layer.