Semiconductor memory device and method of manufacturing the semiconductor memory device

1. A semiconductor memory device, comprising:

a stacked body including interlayer insulating layers and a select line disposed between the interlayer insulating layers;

a core insulating layer formed in the stacked body to penetrate the select line;

a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped area disposed between the select line and a portion of the core insulating layer, wherein the portion of the core insulating layer penetrates the select line;

doped semiconductor patterns disposed between the semiconductor pattern and the interlayer insulating layers; and

a gate insulating layer disposed between the semiconductor pattern and the select line.

2. The semiconductor memory device according to claim 1 , wherein the semiconductor pattern further includes doped areas disposed between the core insulating layer and the doped semiconductor patterns.

3. The semiconductor memory device according to claim 1 , further comprising:

a barrier pattern disposed between the gate insulating layer and the semiconductor pattern and extending to a space between the doped semiconductor patterns and the semiconductor pattern.

4. The semiconductor memory device according to claim 3 , wherein the undoped area extends to a space between the core insulating layer and the doped semiconductor patterns.

5. The semiconductor memory device according to claim 3 , wherein a thickness of the barrier pattern is less than a thickness of the semiconductor pattern and a thickness of each of the doped semiconductor patterns.

6. The semiconductor memory device according to claim 3 , wherein a thickness of the barrier pattern is less than a thickness of the gate insulating layer.

7. The semiconductor memory device according to claim 1 , further comprising:

a capping pattern overlapping the core insulating layer,

wherein the semiconductor pattern extends to surround a sidewall of the capping pattern.

8. The semiconductor memory device according to claim 7 , wherein the capping pattern includes a semiconductor material doped with dopants of a same type as the doped semiconductor pattern.

9. The semiconductor memory device according to claim 7 , wherein the semiconductor pattern includes a doped area surrounding the sidewall of the capping pattern.

10. The semiconductor memory device according to claim 1 , wherein the semiconductor pattern extends along a bottom surface of the core insulating layer.

11. The semiconductor memory device according to claim 1 , wherein the select line is a drain select line.

12. A semiconductor memory device, comprising:

a first stacked body including first interlayer insulating layers and first conductive patterns that are alternately disposed in a stacking direction;

a first channel structure penetrating the first stacked body;

a second stacked body overlapping the first stacked body and including second interlayer insulating layers stacked in the stacking direction and a second conductive pattern disposed between the second interlayer insulating layers;

a second channel structure penetrating the second stacked body to come into contact with the first channel structure; and

a gate insulating layer disposed between the second channel structure and the second conductive pattern,

wherein the second channel structure comprises:

a semiconductor pattern including an undoped area surrounded by the gate insulating layer, and penetrating the second stacked body; and

doped semiconductor patterns disposed between the semiconductor pattern and the second interlayer insulating layers and separated from each other by the gate insulating layer.

13. The semiconductor memory device according to claim 12 , wherein the first channel structure comprises:

a first core insulating layer penetrating the first stacked body; and

a first channel layer surrounding a sidewall of the first core insulating layer.

14. The semiconductor memory device according to claim 13 , wherein the second channel structure extends to an inside of the first core insulating layer and comes into contact with the first channel layer.

15. The semiconductor memory device according to claim 12 , wherein the second channel structure further comprises:

a second core insulating layer penetrating the second stacked body; and

a capping pattern overlapping the first channel structure, wherein the second core insulating layer is interposed between the capping pattern and the first channel structure.

16. The semiconductor memory device according to claim 15 , wherein:

the semiconductor pattern extends along a sidewall of the capping pattern, a sidewall of the second core insulating layer, and a bottom surface of the second core insulating layer, and

the doped semiconductor patterns include a first doped semiconductor pattern extending to a space between the semiconductor pattern and the first channel structure.

17. The semiconductor memory device according to claim 15 , wherein the capping pattern includes a semiconductor material doped with dopants of a same type as the doped semiconductor patterns.

18. The semiconductor memory device according to claim 15 , wherein:

the doped semiconductor patterns include a second doped semiconductor pattern extending to surround a sidewall of the capping pattern, and

the semiconductor pattern further includes a doped area disposed between the capping pattern and the second doped semiconductor pattern.

19. The semiconductor memory device according to claim 12 , wherein the semiconductor pattern further includes doped areas surrounded by the doped semiconductor patterns.

20. The semiconductor memory device according to claim 12 , further comprising:

a barrier pattern extending along a sidewall and a bottom surface of the semiconductor pattern so that the barrier pattern is disposed between the doped semiconductor patterns and the semiconductor pattern and between the gate insulating layers and the semiconductor pattern.

21. The semiconductor memory device according to claim 20 , wherein a thickness of the barrier pattern is less than a thickness of the semiconductor pattern and a thickness of each of the doped semiconductor patterns.

22. The semiconductor memory device according to claim 20 , wherein a thickness of the barrier pattern is less than a thickness of the gate insulating layer.

23. The semiconductor memory device according to claim 12 , further comprising:

a source layer coupled to the first channel structure and overlapping the second stacked body, wherein the first stacked body is interposed between the source layer and the second stacked body;

a bit line coupled to the second channel structure and overlapping the first stacked body, wherein the second stacked body is interposed between the bit line and the first stacked body; and

a peripheral circuit overlapping the second stacked body, wherein the first stacked body and the source layer are interposed between the peripheral circuit and the second stacked body.

24. The semiconductor memory device according to claim 12 , further comprising:

a source layer coupled to the first channel structure and overlapping the second stacked body, wherein the first stacked body is interposed between the source layer and the second stacked body;

a bit line coupled to the second channel structure and overlapping the first stacked body, wherein the second stacked body is interposed between the bit line and the first stacked body; and

a peripheral circuit overlapping the first stacked body, wherein the bit line and the second stacked body are interposed between the peripheral circuit and the first stacked body.