Error-correction encoding method and device, and decoding method and device using channel polarization

1. An encoding device that encodes an information bit sequence of a constant bit length K, to generate a code bit sequence of a constant bit length M×L, the encoding device comprising:

a variable information-length encoder configured to:

input the information bit sequence;

divide the information bit sequence into L information blocks of designated bit lengths according to an information-bit length switching signal; and

perform error-correction encoding on each of the L information blocks to generate L M-bit codes;

a block length converter that converts the L M-bit codes into M L-bit blocks by reordering bits of the L M-bit codes;

a Polar converter that converts the M L-bit blocks to M L-bit codes through channel polarization processing to output a converted M×L-bit code as the code bit sequence; and

an information bit length switch that generates the information bit length switching signal for dividing the information bit sequence into L designated bit lengths which are not necessarily constant, based on channel polarization information of the Polar converter.

2. The encoding device according to claim 1 , wherein the information bit length switch sets the designated bit lengths as a count of integers at positions other than frozen-bit positions of the channel polarization in a set of integers {iM, iM+1, . . . , (i+1) M−1} for each i for I=0, 1, . . . , L−1.

3. The encoding device according to claim 1 , wherein the variable information-length encoder comprises:

M+1 error-correction encoders each inputting different designated bit lengths k (k is an integer equal to or greater than 0 and equal to or smaller than M); and

a selector that selects one from the M+1 error-correction encoders according to the information bit length switching signal,

wherein each of the M+1 error-correction encoders adds redundant bits to an information bit block of a corresponding designated bit length k to generate an M-bit code, and the selector selectively switches an error-correction encoder depending on the designated bit length k corresponding to the information bit length switching signal.

4. A decoding device that inputs an input signal sequence and decodes an information bit sequence from the input signal sequence, the input signal sequence corresponding to a code bit sequence of a constant bit length M×L, wherein an encoding device generates the code bit sequence through error-correction encoding and channel polarization processing on an information bit sequence of a constant bit length K, the decoding device comprising:

M Polar decoding means that decoders configured to:

divide the input signal sequence into M input signal blocks, each input signal block including L input signals;

performs the channel polarization processing on each of the M input signal blocks; and

outputs L Polar decoded signals for each of the M input signal blocks;

a variable information-length decoder configured to:

input a Polar decoded signal according to a designated bit length designated by an information bit length switching signal, from M Polar decoded signal blocks, each Polar decoded signal block including L Polar decoded signals which are output respectively by the M Polar decoding means decoders; and

estimate the information bit sequence according to error-correction decoding scheme; and

an information bit length switch that generates the information bit length switching signal for designating, as the designated bit lengths, information bit lengths included in the M Polar decoded signal blocks output respectively by the M Polar decoders.

5. The decoding device according to claim 4 , wherein the information bit length switch sets the designated bit length as a count of integers at positions other than frozen-bit positions in a Polar encoding scheme corresponding to the Polar decoders, in a set of integers {iM, iM+1, . . . , (i+1) M−1} for each i for I=0, 1, . . . , L−1.

6. The decoding device according to claim 4 , wherein the variable information-length decoder comprises:

M+1 error-correction decoders each outputting different designated bit lengths k (k is an integer equal to or greater than 0 and equal to or smaller than M); and

a selector that selects one from the M+1 error-correction decoders according to the information bit length switching signal,

wherein the M+1 error-correction decoders correspond respectively to M+1 error-correction encoders which generate M-bit codes by adding redundant bits to information bit blocks of designated bit lengths, and the selector selectively switches an error-correction decoder depending on the designated bit length corresponding to the information bit length switching signal.

7. The decoding device according to claim 6 , wherein the M+1 error-correction decoders comprises:

a storage that stores code-trellis information whose size is determined by a k×M generator matrix, wherein a designated bit length k is an integer equal to or greater than 0 and equal to or smaller than M; and

a calculator configured to estimates an information bit sequence of a bit length k according to Viterbi algorithm using the code-trellis information.

8. The decoding device according to claim 4 , wherein the error-correction decoders feeds code bits of a code bit sequence back to the M Polar decoding means for Polar decoding, respectively, the code bit sequence corresponding to the information bit sequence decoded in the M+1 error-correction decoders.

9. An encoding method for encoding an information bit sequence of a constant bit length K, to generate a code bit sequence of a constant bit length M×L, the encoding method comprising:

by a variable information-length encoder,

inputting the information bit sequence;

dividing the information bit sequence into L information blocks of designated bit lengths according to an information-bit length switching signals; and

performing error-correction encoding on each of the L information blocks to generate L M-bit codes;

by a block length converter, converting the L M-bit codes into M L-bit blocks by reordering bits of the L M-bit codes;

by a Polar converter, converting the M L-bit blocks to M L-bit codes through channel polarization processing to output a converted M×L-bit code as the code bit sequence; and

by an information bit length switch, generating the information bit length switching signal for dividing the information bit sequence into L designated bit lengths which are not necessarily constant, based on channel polarization information of the Polar converter.

10. The encoding method according to claim 9 , wherein the information bit length switch sets the designated bit length as a count of integers at positions other than frozen-bit positions of the channel polarization in a set of integers {iM, iM+1, . . . , (i+1) M−1} for each i for I=0, 1, . . . , L−1.

11. The encoding method according to claim 9 , wherein the variable information-length encoder selects one from M+1 error-correction encoders according to the information bit length switching signal, the M+1 error-correction encoders each inputting different designated bit lengths k (k is an integer equal to or greater than 0 and equal to or smaller than M); and

each of the M+1 error-correction encoders adds redundant bits to an information bit block of a corresponding designated bit length k to generate M-bit code, and selectively switches an error-correction encoder depending on the designated bit length k corresponding to the information bit length switching signal.

12. A decoding method for inputting an input signal sequence and decoding an information bit sequence from the input signal sequence, the input signal sequence corresponding to a code bit sequence of a constant bit length M×L, wherein an encoding device generates the code bit sequence through error-correction encoding and channel polarization processing on an information bit sequence of a constant bit length K, the decoding method comprising:

by M Polar decoders, dividing the input signal sequence into M input signal blocks, each input signal block including L input signals, performing the channel polarization processing on each of the M input signal blocks, and outputting L Polar decoded signals for each of the M input signal blocks;

by a variable information-length decoder, inputting a Polar decoded signal according to a designated bit length designated by an information bit length switching signal, from M Polar decoded signal blocks, each Polar decoded signal block including L Polar decoded signals which are output respectively by the M Polar decoders, and estimating the information bit sequence according to error-correction decoding scheme; and

by an information bit length switch, generating the information bit length switching signal for designating, as the designated bit length, an information bit length included in the M Polar decoded signal blocks output respectively by the M Polar decoders.

13. The decoding method according to claim 12 , wherein the information bit length switch sets the designated bit length as a count of integers at positions other than frozen-bit positions in a Polar encoding scheme corresponding to the Polar decoding means, in a set of integers {iM+1, . . . , (i+1) M−1} for each i for I=0, 1, . . . , L−1.

14. The decoding method according to claim 12 , wherein the variable information-length decoder selects one from M+1 error-correction decoders according to the information bit length switching signal, the M+1 error-correction decoders each outputting different designated bit lengths k (k is an integer equal to or greater than 0 and equal to or smaller than M);

the M+1 error-correction decoders correspond respectively to M+1 error-correction encoders which generate M-bit codes by adding redundant bits to information bit blocks of designated bit lengths; and

an error-correction decoder is selectively switched depending on the designated bit length corresponding to the information bit length switching signal.

15. The decoding method according to claim 14 , wherein at each of the M+1 error-correction decoders,

storing code-trellis information whose size is determined by a k×M generator matrix, wherein a designated bit length k is an integer equal to or greater than 0 and equal to or smaller than M; and

estimating an information bit sequence of a bit length k according to Viterbi algorithm using the code-trellis information.

16. The decoding method according to claim 12 , wherein the variable information-length decoder feeds code bits of a code bit sequence back to the M Polar decoding means for Polar decoding, respectively, the code bit sequence corresponding to the information bit sequence decoded in the M+1 error-correction decoders.