IP Library Granted Patent US 11,482,597
Granted Patent B2
US 11,482,597 · App. 16/959,153 · Granted Oct 25, 2022

Semiconductor wafer having epitaxial layer

Inventors: Norbert Werner (Tengling, DE); Christian Hager (Kastl, DE)
Assignee: SILTRONIC AG
H01L29/16C23C16/4585C30B29/06H01L21/02381H01L21/02532
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,482,597
App. No.
16/959,153
Granted
Oct 25, 2022
Kind
B2
Abstract

A semiconductor wafer of monocrystalline silicon. The semiconductor wafer having: a substrate wafer of monocrystalline silicon; and a layer of monocrystalline silicon that lies on a front side of the substrate wafer. The substrate wafer has a crystal orientation. An averaged front side-based ZDD of the semiconductor wafer, with a division of a surface of an epitaxial layer into 16 sectors and an edge exclusion of 1 mm, is not less than −30 nm/mm 2 and not more than 0 nm/mm 2 . An ESFQR max of the semiconductor wafer, with an edge exclusion of 1 mm and 72 sectors each with a length of 30 mm, is at most 10 nm.

Claims (13)

1. A semiconductor wafer of monocrystalline silicon, the semiconductor wafer comprising:

a substrate wafer of monocrystalline silicon; and

a layer of monocrystalline silicon that lies on a front side of the substrate wafer,

wherein the substrate wafer has a crystal orientation,

wherein an averaged front side-based double derivative of a height Z (ZDD) of the semiconductor wafer, with a division of a surface of an epitaxial layer into 16 sectors and an edge exclusion of 1 mm, is not less than −30 nm/mm2 and not more than 0 nm/mm 2 , and

wherein a maximum edge site front least-squares range (ESFQR max ) of the semiconductor wafer, with an edge exclusion of 1 mm and 72 sectors each with a length of 30 mm, is at most 10 nm.

2. The semiconductor wafer of monocrystalline silicon as claimed in claim 1 , wherein the crystal orientation is a {100} orientation.

3. The semiconductor wafer of monocrystalline silicon as claimed in claim 1 , wherein the crystal orientation is a {110} orientation.

4. The semiconductor wafer of monocrystalline silicon as claimed in claim 1 , wherein a diameter of the semiconductor wafer is not less than 300 mm.

5. The semiconductor wafer of monocrystalline silicone as claimed in claim 1 , wherein ZDD is determined according to SEMI M68-1015 and ESFQR max is determined according to SEMI M67-1015.

6. The semiconductor wafer of monocrystalline silicone as claimed in claim 1 , further comprising an oxide layer at an edge of the substrate wafer.

7. The semiconductor wafer of monocrystalline silicone as claimed in claim 1 , further comprising an oxide layer on a back side of the semiconductor wafer.

8. The semiconductor wafer of monocrystalline silicone as claimed in claim 1 , wherein the layer of monocrystalline silicon is not present at an edge region of the semiconductor wafer or on a back side of the semiconductor wafer.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2020
From: WERNER, NORBERT; HAGER, CHRISTIAN
To: SILTRONIC AG
Reel/Frame 053081/0066 →