IP Library Granted Patent US 11,350,056
Granted Patent B2
US 11,350,056 · App. 16/965,191 · Granted May 31, 2022

Image sensor and electronic device

Inventors: Katzutoshi Tomita (Kanagawa, JP); Yusuke Ikeda (Tokyo, JP); Sachio Akebono (Kanagawa, JP); Takashi Moue (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H04N5/378H04N5/3745H04N5/3698
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Quick Facts
Patent No.
US 11,350,056
App. No.
16/965,191
Granted
May 31, 2022
Kind
B2
Abstract

An image sensor including a pixel array section in which a plurality of pixels including photoelectric conversion units is disposed, and a comparator that compares an analog pixel signal output from the pixels to a predetermined reference signal, and outputs a comparison result according to a signal level of the pixel signal. The comparator includes differential pair transistors, a first load transistor connected in series with a first transistor of the differential pair, and a second load transistor connected in series with a second transistor of the differential pair. The first transistor of the differential pair accepts a signal obtained by combining the pixel signal and the predetermined reference signal as a gate input, the second transistor of the differential pair accepts a predetermined voltage as a gate input. In addition, a capacitance unit is connected between a common connection node of the first transistor of the differential pair and the first load transistor, and a node of the predetermined voltage.

Claims (72)

1. An image sensor comprising:

a pixel array section in which a plurality of pixels including photoelectric conversion units is disposed; and a comparator that compares an analog pixel signal output from the pixels to a predetermined reference signal, and outputs a comparison result according to a signal level of the pixel signal, wherein

the comparator includes

differential pair transistors,

a first load transistor connected in series with a first transistor of the differential pair, and

a second load transistor connected in series with a second transistor of the differential pair,

the first transistor of the differential pair accepts a signal obtained by combining the pixel signal and the predetermined reference signal as a gate input,

the second transistor of the differential pair accepts a predetermined voltage as a gate input, and

a capacitance unit is connected between a common connection node of the first transistor of the differential pair and the first load transistor, and a node of the predetermined voltage.

2. The image sensor according to claim 1 , wherein

the pixel signal and the predetermined reference signal are accepted as the gate input of the first transistor of the differential pair through respective capacitance elements.

3. The image sensor according to claim 1 , wherein

the predetermined voltage is a voltage of any value.

4. The image sensor according to claim 1 , wherein

a capacitance value of the capacitance unit is variable.

5. The image sensor according to claim 4 , wherein

the capacitance unit contains a variable capacitance element having a variable capacitance value.

6. The image sensor according to claim 4 , wherein

the capacitance unit contains a plurality of capacitance elements and a toggle switch that selects at least one of the plurality of capacitance elements on a basis of a control signal.

7. The image sensor according to claim 6 , wherein

the plurality of capacitance elements are capacitance elements having the same capacitance values as each other.

8. The image sensor according to claim 6 , wherein

the plurality of capacitance elements are capacitance elements having different capacitance values from each other.

9. The image sensor according to claim 6 , wherein

the capacitance unit includes an isolation circuit that electrically isolates a control line that supplies the control signal from the toggle switch.

10. The image sensor according to claim 9 , wherein

the isolation circuit is an inverter circuit or a buffer circuit.

11. The image sensor according to claim 1 , wherein

the first load transistor is configured as a diode connection.

12. The image sensor according to claim 11 , wherein

the first load transistor and the second load transistor form a current mirror circuit.

13. The image sensor according to claim 11 , wherein

a common connection node of the second transistor of the differential pair and the second load transistor is an output node.

14. The image sensor according to claim 1 , wherein

the comparator is provided in correspondence with a pixel column of the pixel array section, and is used in an analog-to-digital converter that converts the analog pixel signal output from the pixels into a digital signal.

15. The image sensor according to claim 14 , wherein

the analog-to-digital converter is provided with respect to each pixel column or with respect to a plurality of pixel columns of the pixel array section.

16. An electronic device comprising an image sensor, the image sensor including:

a pixel array section in which a plurality of pixels including photoelectric conversion units is disposed; and a comparator that compares an analog pixel signal output from the pixels to a predetermined reference signal, and outputs a comparison result according to a signal level of the pixel signal, wherein

the comparator includes

differential pair transistors,

a first load transistor connected in series with a first transistor of the differential pair, and

a second load transistor connected in series with a second transistor of the differential pair,

the first transistor of the differential pair accepts a signal obtained by combining the pixel signal and the predetermined reference signal as a gate input,

the second transistor of the differential pair accepts a predetermined voltage as a gate input, and

a capacitance unit is connected between a common connection node of the first transistor of the differential pair and the first load transistor, and a node of the predetermined voltage.

17. An image sensor comprising:

a pixel array section in which a plurality of pixels including photoelectric conversion units is disposed; and a comparator that compares an analog pixel signal output from the pixels to a predetermined reference signal, and outputs a comparison result according to a signal level of the pixel signal, wherein

the comparator includes a first amplification unit and a second amplification unit connected in cascade,

the first amplification unit includes

differential pair transistors,

a first load transistor connected in series with a first transistor of the differential pair, and

a second load transistor connected in series with a second transistor of the differential pair,

the first transistor of the differential pair accepts a signal obtained by combining the pixel signal and the predetermined reference signal as a gate input,

the second transistor of the differential pair accepts a predetermined voltage as a gate input, and

the second amplification unit includes

a first capacitance unit connected between an output node and a node of the predetermined voltage.

18. The image sensor according to claim 17 , wherein

the first amplification unit includes a second capacitance unit connected between a common connection node of the first transistor of the differential pair and the first load transistor, and the node of the predetermined voltage.

19. The image sensor according to claim 17 , further comprising:

a clamp circuit that clamps a potential of the output node of the first amplification unit to a predetermined potential when an output of the second amplification unit inverts.

20. An electronic device comprising an image sensor, the image sensor including:

a pixel array section in which a plurality of pixels including photoelectric conversion units is disposed; and a comparator that compares an analog pixel signal output from the pixels to a predetermined reference signal, and outputs a comparison result according to a signal level of the pixel signal, wherein

the comparator includes a first amplification unit and a second amplification unit connected in cascade,

the first amplification unit includes

differential pair transistors,

a first load transistor connected in series with a first transistor of the differential pair, and

a second load transistor connected in series with a second transistor of the differential pair,

the first transistor of the differential pair accepts a signal obtained by combining the pixel signal and the predetermined reference signal as a gate input,

the second transistor of the differential pair accepts a predetermined voltage as a gate input, and

the second amplification unit includes

a capacitance unit connected between an output node and a node of the predetermined voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2020
From: TOMITA, KATZUTOSHI; IKEDA, YUSUKE; AKEBONO, SACHIO; MOUE, TAKASHI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 053741/0275 →
Priority Claims (2)
JP JP2018-016994 · Feb 2, 2018 · national
JP JP2018-120557 · Jun 26, 2018 · national
Continuity (1)
Related Publication 20220094871A1 · Mar 24, 2022
Cited By (2)
US 12,581,221 US 12,739,535