Semiconductor device and manufacturing method thereof
View Patent ↗Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer; a group III-V dielectric layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the second nitride semiconductor layer; and a first passivation layer disposed on the group III-V dielectric layer, wherein the group III-V dielectric layer is separated from the gate electrode by the first passivation layer.
1. A semiconductor device, comprising:
a substrate;
a first nitride semiconductor layer on the substrate;
a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer;
a group III-V dielectric layer disposed on the second nitride semiconductor layer;
a gate electrode disposed on the second nitride semiconductor layer; and
a first passivation layer disposed on the group III-V dielectric layer,
wherein the group III-V dielectric layer is separated from the gate electrode by the first passivation layer, and the gate electrode comprises a protrusion in direct contact with the second nitride semiconductor layer.
2. The semiconductor device according to claim 1 , wherein the first passivation layer extends along the group III-V dielectric layer.
3. The semiconductor device according to claim 1 , wherein the first passivation layer covers the sidewall of the group III-V dielectric layer.
4. The semiconductor device according to claim 1 , wherein the first passivation layer surrounds the group III-V dielectric layer.
5. The semiconductor device according to claim 1 , wherein the first passivation layer is in direct contact with the group III-V dielectric layer.
6. The semiconductor device according to claim 1 , wherein the first passivation layer is in direct contact with the sidewall of the group III-V dielectric layer.
7. The semiconductor device according to claim 1 , wherein the first passivation layer extends on the second nitride semiconductor layer.
8. The semiconductor device according to claim 1 , wherein the first passivation layer is in direct contact with the gate electrode.
9. The semiconductor device according to claim 1 , wherein the first passivation layer has a first length between the group III-V dielectric layer and the gate electrode, and wherein the first length ranges between approximately 100 nm and approximately 500 nm.
10. The semiconductor device according to claim 9 , wherein the first passivation layer has a second length between the group III-V dielectric layer and the gate electrode, and wherein the second length is different from the first length.
11. The semiconductor device according to claim 1 , wherein the gate electrode includes a step shape structure.
12. The semiconductor device according to claim 1 , wherein the gate electrode includes a funnel shape structure.
13. The semiconductor device according to claim 1 , wherein the group III-V dielectric layer includes aluminum nitride (AlN).
14. The semiconductor device according to claim 1 , wherein the group III-V dielectric layer includes boron nitride (BN).
15. The semiconductor device according to claim 1 , wherein the group III-V dielectric layer is devoid of oxygen.
16. The semiconductor device according to claim 1 , wherein the surface state density of the second nitride semiconductor layer ranges between approximately 10 10 cm −2 and approximately 10 12 cm −2 .
17. The semiconductor device according to claim 1 , further comprising:
an oxide layer disposed between the group III-V dielectric layer and the first passivation layer.
18. The semiconductor device according to claim 17 , wherein the oxide layer comprises aluminum oxynitride (AlON).
19. The semiconductor device according to claim 17 , wherein the oxide layer has a thickness less than 1 nm.
20. The semiconductor device according to claim 1 , further comprising:
a second passivation layer between on the group III-V dielectric layer and the first passivation layer,
wherein the first passivation layer and the second passivation layer include non-group III-V dielectric materials.
21. The semiconductor device according to claim 1 , wherein a top of the gate electrode is flush with an upper surface of the first passivation layer, the gate electrode comprises a first sidewall, a second sidewall parallel to the first sidewall, and a bottom wall; the first sidewall and the second sidewall penetrate through the first passivation layer and a part of the group III-V dielectric layer; the bottom wall comprises the protrusion in direct contact with the second nitride semiconductor layer, and the protrusion is within the group III-V dielectric layer.