Deterministic stellar built-in self test
A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.
1. A system for testing a circuit, comprising:
scan chains comprising scan cells, the scan chains configured, in a test mode, to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses;
a controller comprising storage circuitry, the controller configured to generate a bit-inverting signal based on child test pattern information stored in the storage circuitry; and
bit-inverting circuitry coupled to the controller, the bit-inverting circuitry configured to generate a child test pattern by inverting a plurality of bits of a parent test pattern during a shift operation based on the bit-inverting signal, wherein locations of the plurality of bits are associated with a plurality of shift clock cycles for bit inverting, the plurality of shift clock cycles for bit inverting occurring every m shift clock cycles, m representing a distance between successive bit-inverting time frames, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles for bit inverting in the shift operation,
and wherein the parent test pattern and the location of the plurality of shift clock cycles for bit inverting in the shift operation are determined by a test pattern generation software tool, the test pattern generation software tool performing a pattern generation process comprising: performing a circuit structural analysis first to identify supergates, running an automatic test pattern generation (ATPG) process using the supergates to determine parent test patterns, and generating child test patterns for the parent test patterns.
2. The system recited in claim 1 , wherein m is the same for all of child patterns for all of parent test patterns of a test set.
3. The system recited in claim 1 , wherein the pattern generation process further comprises: performing pattern reordering, and saving effective child test patterns.
4. The system recited in claim 1 , further comprising:
test pattern decompressing circuitry, test pattern decompressing circuitry configured to decompress compressed parent test pattern into the parent test pattern.
5. The system recited in claim 4 , wherein the inverting bits is performed in the test pattern decompressing circuitry.
6. The system recited in claim 4 , wherein the test pattern decompressing circuitry comprises a ring generator and a phase shifter.
7. The system recited in claim 6 , wherein the inverting bits is performed by XOR gates inserted between the ring generator and the phase shifter.
8. The system recited in claim 1 , wherein the storage circuitry comprises a first register for storing information of m and a second register for storing information of location of the plurality of shift clock cycles for bit inverting in the shift operation.
9. The system recited in claim 8 , wherein the controller further comprises a down counter, the down counter being coupled to outputs of the second register, and the bit-inverting signal is generated based on combining outputs of the down counter and outputs of the first register.
10. One or more computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising:
creating a system in a circuit design for testing a circuit fabricated according to the circuit design, the system comprising:
scan chains comprising scan cells, the scan chains configured, in a test mode, to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses;
a controller comprising storage circuitry, the controller configured to generate a bit-inverting signal based on child test pattern information stored in the storage circuitry; and
bit-inverting circuitry coupled to the controller, the bit-inverting circuitry configured to generate a child test pattern by inverting a plurality of bits of a parent test pattern during a shift operation based on the bit-inverting signal to, wherein locations of the plurality of bits are associated with a plurality of shift clock cycles for bit inverting, the plurality of shift clock cycles for bit inverting occurring every m shift clock cycles, m representing a distance between successive bit-inverting time frames, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles for bit inverting in the shift operation,
and wherein the parent test pattern and the location of the plurality of shift clock cycles for bit inverting in the shift operation are determined by a test pattern generation software tool, the test pattern generation software tool performing a pattern generation process comprising: performing a circuit structural analysis first to identify supergates, running an automatic test pattern generation (ATPG) process using the supergates to determine parent test patterns, and generating child test patterns for the parent test patterns.
11. The one or more computer-readable media recited in claim 10 , wherein m is the same for all of child patterns for all of parent test patterns of a test set.
12. The one or more computer-readable media recited in claim 10 , wherein the pattern generation process further comprises: performing pattern reordering, and saving effective child test patterns.
13. The one or more computer-readable media recited in claim 10 , wherein the system further comprises: test pattern decompressing circuitry, test pattern decompressing circuitry configured to decompress compressed parent test pattern into the parent test pattern.
14. The one or more computer-readable media recited in claim 13 , wherein the inverting bits is performed in the test pattern decompressing circuitry.
15. The one or more computer-readable media recited in claim 13 , wherein the test pattern decompressing circuitry comprises a ring generator and a phase shifter.
16. The one or more computer-readable media recited in claim 15 , wherein the inverting bits is performed by XOR gates inserted between the ring generator and the phase shifter.
17. The one or more computer-readable media recited in claim 10 , wherein the storage circuitry comprises a first register for storing information of m and a second register for storing information of location of the plurality of shift clock cycles for bit inverting in the shift operation.
18. The one or more computer-readable media recited in claim 17 , wherein the controller further comprises a down counter, the down counter being coupled to outputs of the second register, and the bit-inverting signal is generated based on combining outputs of the down counter and outputs of the first register.