Flexible isometric decompressor architecture for test compression
A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.
1. A system for testing a circuit, comprising:
scan chains comprising scan cells, the scan chains configured, in a test mode, to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses;
a controller comprising first storage circuitry, second storage circuitry, and a control signal generator, the first storage circuitry comprising circuitry configured to store operational mode information, the second storage circuitry comprising circuitry configured to store information of a hold-toggle pattern, and the control signal generator configured to generate a control signal based on the operational mode information and the hold-toggle pattern, wherein the operational mode information determines whether a scan chain operates in a full-toggle mode or in a hold-toggle mode during a shift period, the hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles scan chains operating in the hold-toggle mode receive bits based on corresponding bits of a test pattern during the shift period, and the hold-toggle pattern repeats multiple times during the shift period, the shift period being a period when the test pattern is being shifted into the scan chains; and
hold-toggle circuitry coupled to the controller and configured to allow, according to the control signal, some scan chains in the scan chains to operate in the full-toggle mode and some other scan chains in the scan chains to operate in the hold-toggle mode during the shift period.
2. The system recited in claim 1 , further comprising:
a decompressor, outputs of the hold-toggle circuitry being coupled to inputs of the decompressor or inputs of an expander in the decompressor.
3. The system recited in claim 2 , wherein the decompressor comprises a ring generator and the expander is a phase shifter.
4. The system recited in claim 1 , wherein the hold-toggle circuitry comprises a plurality of subunits, each of the plurality of subunits being controlled by a bit of the control signal.
5. The system recited in claim 1 , wherein the second storage circuitry comprises a circular shift register.
6. The system recited in claim 5 , wherein the circular shift register has 32 or fewer than 32 bits.
7. The system recited in claim 1 , wherein the first storage circuitry comprises one or two pairs of register and decoder.
8. The system recited in claim 7 , wherein the decoder is a one-hot decoder.
9. The system recited in claim 1 , wherein the control signal generator comprises a plurality of subunits, each subunit combining an output of the second storage circuitry with one or more outputs of the first storage circuitry.
10. The system recited in claim 9 , wherein the plurality of subunits are OR gates.
11. One or more non-transitory computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising:
creating a system in a circuit design for testing a circuit fabricated according to the circuit design, the system comprising:
scan chains comprising scan cells, the scan chains configured, in a test mode, to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses;
a controller comprising first storage circuitry, second storage circuitry, and a control signal generator, the first storage circuitry comprising circuitry configured to store operational mode information, the second storage circuitry comprising circuitry configured to store information of a hold-toggle pattern, and the control signal generator configured to generate a control signal based on the operational mode information and the hold-toggle pattern, wherein the operational mode information determines whether a scan chain operates in a full-toggle mode or in a hold-toggle mode during a shift period, the hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles scan chains operating in the hold-toggle mode receive bits based on corresponding bits of a test pattern during the shift period, and the hold-toggle pattern repeats multiple times during the shift period, the shift period being a period when the test pattern is being shifted into the scan chains; and
hold-toggle circuitry coupled to the controller and configured to allow, according to the control signal, some scan chains in the scan chains to operate in the full-toggle mode and some other scan chains in the scan chains to operate in the hold-toggle mode during the shift period.
12. The one or more non-transitory computer-readable media recited in claim 11 , wherein the system further comprises:
a decompressor, outputs of the hold-toggle circuitry being coupled to inputs of the decompressor or inputs of an expander in the decompressor.
13. The one or more non-transitory computer-readable media recited in claim 12 , wherein the decompressor comprises a ring generator and the expander is a phase shifter.
14. The one or more non-transitory computer-readable media recited in claim 11 , wherein the hold-toggle circuitry comprises a plurality of subunits, each of the plurality of subunits being controlled by a bit of the control signal.
15. The one or more non-transitory computer-readable media recited in claim 11 , wherein the second storage circuitry comprises a circular shift register.
16. The one or more non-transitory computer-readable media recited in claim 15 , wherein the circular shift register has 32 or fewer than 32 bits.
17. The one or more non-transitory computer-readable media recited in claim 11 , wherein the first storage circuitry comprises one or two pairs of register and decoder.
18. The one or more non-transitory computer-readable media recited in claim 17 , wherein the decoder is a one-hot decoder.
19. The one or more non-transitory computer-readable media recited in claim 11 , wherein the control signal generator comprises a plurality of subunits, each subunit combining an output of the second storage circuitry with one or more outputs of the first storage circuitry.
20. The one or more non-transitory computer-readable media recited in claim 19 , wherein the plurality of subunits are OR gates.