Display panel and display device
View Patent ↗The present disclosure provides a display panel, which includes a plurality of data lines, a plurality of scan lines, and a plurality of pixels, a main scan electrode and a branch scan electrode of the same scan line are electrically connected, and a pixel electrode partially overlaps the branch scan electrode to form a storage capacitance.
1. A display panel, wherein the display panel comprises:
a plurality of data lines;
a plurality of scan lines, each of the scan lines comprises a main scan electrode and a branch scan electrode, the main scan electrode and the branch scan electrode of a same scan line are electrically connected, and at least a part of branch scan electrodes extend along an extending direction of a data line and are adjacent to the data line; and
a plurality of pixels, each of the pixels comprises a pixel electrode, the pixel electrode partially overlaps the branch scan electrode to form a storage capacitance;
wherein the pixel electrode partially overlaps the branch scan electrode and the main scan electrode of a post-stage scan line; the pixel further comprises a switching component, the switching component comprises a source electrode, a drain electrode, and a gate electrode, a parasitic capacitance Cgs is formed between the source electrode and the gate electrode; when the display panel is in an operating state, a scan signal on each of the scan lines comprises a high level Vgh, a first low level Vgl1, and a second low level Vgl2, the high level Vgh is higher than the first low level Vgl1, the first low level Vgl1 is higher than the second low level Vgl2, the second low level Vgl2 is located on a falling edge side of the high level Vgh, and a second duration of the second low level Vgl2 is equivalent to a first duration of the high level Vgh, a high level falling edge of the scan signal on a current-stage scan line synchronizes with a high level rising edge of the scan signal on the post-stage scan line; the storage capacitance Cst satisfies Cst=(Vgh−Vgl1)×Cgs/(Vgl1−Vgl2).
2. The display panel according to claim 1 , wherein the pixel electrode partially overlaps the main scan electrode and the branch scan electrode to form the storage capacitance.
3. The display panel according to claim 2 , wherein the pixel electrode partially overlaps two of the branch scan electrodes, and the two branch scan electrodes are respectively defined at two sides of the pixel electrode.
4. A display panel, wherein the display panel comprises:
a plurality of data lines;
a plurality of scan lines, each of the scan lines comprises a main scan electrode and a branch scan electrode, the main scan electrode and the branch scan electrode of a same scan line are electrically connected, and at least a part of branch scan electrodes extend along an extending direction of a data line and are adjacent to the data line; and
a plurality of pixels, each of the pixels comprises a pixel electrode, the pixel electrode partially overlaps the branch scan electrode to form a storage capacitance;
wherein the pixel electrode partially overlaps the main scan electrode and the branch scan electrode to form the storage capacitance;
the pixel electrode partially overlaps the branch scan electrode and the main scan electrode of a fore-stage scan line;
the pixel further comprises a switching component, the switching component comprises a source electrode, a drain electrode, and a gate electrode, a parasitic capacitance Cgs is formed between the source electrode and the gate electrode;
when the display panel is in an operating state, a scan signal on each of the scan lines comprise a high level Vgh, a first low level Vgl1, and a second low level Vgl2, the high level Vgh is higher than the first low level Vgl1, the first low level Vgl1 is higher than the second low level Vgl2, the second low level Vgl2 is located on a falling edge side of the high level Vgh, and a second duration of the second low level Vgl2 is twice of or equivalent to a first duration of the high level Vgh, a high level falling edge of the scan signal on the fore-stage scan line synchronizes with a high level rising edge of the scan signal on the current-stage scan line; the storage capacitance Cst satisfies Cst=(Vgh−Vgl1)×Cgs/(Vgl1−Vgl2).
5. A display panel, wherein the display panel comprises:
a plurality of data lines;
a plurality of scan lines, each of the scan lines comprises a main scan electrode and a branch scan electrode, the main scan electrode and the branch scan electrode of a same scan line are electrically connected, and at least a part of branch scan electrodes extend along an extending direction of a data line and are adjacent to the data line; and
a plurality of pixels, each of the pixels comprises a pixel electrode, the pixel electrode partially overlaps the branch scan electrode to form a storage capacitance;
wherein the pixel electrode partially overlaps the branch scan electrode and the main scan electrode of the fore-stage scan line;
the pixel further comprises a switching component, the switching component comprises a source electrode, a drain electrode, and a gate electrode, a parasitic capacitance Cgs is formed between the source electrode and the gate electrode;
when the display panel is in an operating state, a scan signal on each of the scan lines comprise a high level Vgh, a first low level Vgl1, and a second low level Vgl2, the high level Vgh is higher than the first low level Vgl1, the first low level Vgl1 is higher than the second low level Vgl2, the second low level Vgl2 is located on a falling edge side of the high level Vgh, and a second duration of the second low level Vgl2 is twice of or equivalent to a first duration of the high level Vgh, a high level falling edge of the scan signal on the fore-stage scan line synchronizes with a high level rising edge of the scan signal on the current-stage scan line; the storage capacitance Cst satisfies Cst=(Vgh−Vgl1)×Cgs/(Vgl1−Vgl2).