IP Library Granted Patent US 11,258,023
Granted Patent B1
US 11,258,023 · App. 16/985,657 · Granted Feb 22, 2022

Resistive change elements using passivating interface gaps and methods for making same

Inventors: Mark Ramsbey (Sunnyvale, CA); Thomas Rueckes (Byfield, MA); Tatsuya Yamaguchi (Yamanashi, JP); Syuji Nozawa (Yamanashi, JP); Nagisa Sato (Tokyo, JP)
Assignee: Nantero, Inc.
H01L51/107H01L27/285H01L51/0003H01L51/0017H01L51/0048H01L51/0591
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Quick Facts
Patent No.
US 11,258,023
App. No.
16/985,657
Granted
Feb 22, 2022
Kind
B1
Abstract

A method to fabricate a resistive change element. The method may include forming a stack over a substrate. The stack may include a conductive material, a resistive change material, a first surface, and a second surfaces opposite the first surface. The method may further include depositing a first material over the stack such that the first material directly contacts at least one of the first surface and the second surface of the stack. The method may also include after depositing the first material, forming a second material over the first material and evaporating a portion of the first material through the second material to create a gap between the second material and the at least one of the first surface and the second surface of the stack.

Claims (52)

1. A method to fabricate a resistive change element, said method comprising:

forming a stack over a substrate, said stack including a conductive material, a resistive change material, a first surface, and a second surfaces opposite said first surface;

depositing a first material over said stack such that said first material directly contacts at least one of said first surface and said second surface of said stack;

after depositing said first material, forming a second material over said first material; and

evaporating a portion of said first material through said second material to create a gap between said second material and said at least one of said first surface and said second surface of said stack.

2. The method of claim 1 , said resistive change material is a nanotube fabric and said resistive change material is deposited by a spin coating operation.

3. The method of claim 1 , wherein one of a gas or a vacuum is in said gap between said second material and said at least one of said first surface and said second surface of said stack.

4. The method of claim 1 , wherein said first material is a polymer material and said second material is an oxide material.

5. The method of claim 1 , wherein said forming said second material is performed at a first temperature, said evaporating said portion of said first material is performed at a second temperature, and said first temperature is lower than said second temperature.

6. The method of claim 1 , further comprising etching said first material before depositing said second material, said etching including removing said first material from a third surface of said stack to expose said third surface of said stack.

7. The method of claim 6 , wherein said stack is formed over a first surface of said substrate, said third surface of said stack is substantially parallel to said first surface of said substrate and said first surface and said second surface of said stack are substantially perpendicular to said first surface of said substrate.

8. The method of claim 1 , wherein said conductive material is a first electrode of said resistive change element and said method further comprises:

forming a second electrode on a first side of said resistive change element that is opposite a second side of said resistive change element adjacent to said first electrode;

depositing a second resistive change material between said first electrode and said second electrode; and

forming an insulator material over said first electrode such that said first electrode is between said second resistive change material and said insulator material and said first material is deposited over said insulator material.

9. The method of claim 1 , wherein depositing said first material over said stack includes depositing said first material into a portion of said resistive change material and said portion of said first material evaporated includes said first material in said portion of said resistive change material.

10. A method to fabricate a memory element, said method comprising:

forming a first conductive material over a substrate;

depositing a resistive change material over said first conductive material;

forming a second conductive material over said resistive change material;

exposing a first surface and a second surface of said resistive change material while said resistive change material remains between said first conductive material and said second conductive material;

after exposing said first surface and said second surface of said resistive change material, depositing an evaporative material in direct contact with said exposed first surface and said exposed second surface of said resistive change material;

after depositing said evaporative material, forming a cover material over said evaporative material; and

evaporating a portion of said evaporative material through said cover material to create a gap between said cover material and said first surface and said second surface of said resistive change material.

11. The method of claim 10 , wherein exposing said first surface and said second surface of said resistive change material includes etching said second conductive material and said resistive change material to expose said first surface and a second surface of said resistive change material, said first surface and said second surfaces being sidewalls of said resistive change material.

12. The method of claim 11 , wherein said depositing said evaporative material includes depositing said evaporative material into a portion of said resistive change material and said portion of said evaporative material that evaporates includes said evaporative material in said portion of said resistive change material.

13. The method of claim 12 , said resistive change material is a nanotube fabric and said resistive change material is deposited by a spin coating operation.

14. The method of claim 12 , further comprising etching said evaporative material before forming said cover material.

15. The method of claim 14 , wherein etching said evaporative material results in a thickness of said evaporative material in direct contact with said second conductive material being less than a thickness of said evaporative material in direct contact with said resistive change material.

16. The method of claim 14 , further comprising:

forming a second insulative material over said cover material; and

depositing a third insulative material over said second insulative material, wherein said second insulative material is different from said third insulative material.

17. The method of claim 16 , further comprising:

forming an opening through said third insulative material, said second insulative material, said cover material, and said insulative material to expose said second conductive material; and

depositing a third conductive material into said opening, said second conductive material forming an electrode for said memory element.

18. The method of claim 14 , further comprising forming an insulator material over said second conductive material such that said insulator material is between said second conductive material and said evaporative material.

19. The method of claim 18 , wherein etching said evaporative material includes exposing said insulator material such that said cover material directly contacts said insulator material.

20. The method of claim 10 , wherein said forming said cover material is performed at a first temperature, said evaporating said portion of said evaporative material is performed at a second temperature, and said first temperature is lower than said second temperature.

21. The method of claim 10 , further comprising depositing a second resistive change material between said resistive change material and said second conductive material.

22. The method of claim 10 , wherein said evaporative material is a polymer material and said cover material is an oxide material.

23. A method to fabricate a memory element, said method comprising:

forming a first electrode over a substrate;

depositing a resistive change material over said first electrode;

forming a second electrode over said resistive change material;

etching said second electrode and said resistive change material to expose a first surface and a second surface of said resistive change material, said first surface and said second surface of said resistive change material being substantially perpendicular to a first surface of said substrate;

after exposing said first surface and said second surface of said resistive change material, depositing an evaporative material in direct contact with said exposed first surface and said exposed second surface of said resistive change material, depositing said evaporative material including depositing said evaporative material into a portion of said resistive change material;

etching said evaporative material to at least remove said evaporative material over said second electrode;

after etching said evaporative material, forming a cover material over and directly in contact with said evaporative material, said forming of said cover material occurring at a first temperature;

evaporating a portion of said evaporative material through said cover material at a second temperature to create a gap between said cover material and said first surface and said second surface of said resistive change material and to remove said evaporative material in said portion of said resistive change material, the second temperature being higher than the first temperature;

after evaporating said portion of said evaporative material; depositing a second insulative material over said cover material;

forming an opening through said second insulative material and said cover material to expose said second electrode; and

depositing a conductive material into said opening, the conductive material electrically coupling to said second electrode.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2022
From: RAMSBEY, MARK; RUECKES, THOMAS
To: NANTERO, INC.
Reel/Frame 058577/0466 →
RELEASE OF SECURITY INTEREST Recorded Jul 14, 2021
From: SILICON VALLEY BANK
To: NANTERO, INC.
Reel/Frame 056854/0901 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2021
From: NANTERO, INC.
To: ZEON CORPORATION
Reel/Frame 056789/0932 →
CONFIRMATORY LICENSE Recorded Apr 23, 2021
From: NANTERO, INC.
To: ZEON CORPORATION
Reel/Frame 056032/0549 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2020
From: YAMAGUCHI, TATSUYA; SATO, NAGISA; NOZAWA, SYUJI
To: TOKYO ELECTRON LIMITED
Reel/Frame 054415/0155 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Nov 11, 2020
From: NANTERO, INC.
To: SILICON VALLEY BANK
Reel/Frame 054383/0632 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2020
From: YAMAGUCHI, TATSUYA; SATO, NAGISA; NOZAWA, SYUJI
To: TOKYO ELECTRON LIMITED
Reel/Frame 053973/0713 →