Conductive via of integrated circuitry, memory array comprising strings of memory cells, method of forming a conductive via of integrated circuitry, and method of forming a memory array comprising strings of memory cells
A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalk of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.
1. A method used in forming a conductive via of integrated circuitry, comprising:
forming a lining laterally over sidewalls of an elevationally-elongated opening, the lining comprising elemental-form silicon;
ion implanting the elemental-form silicon of an uppermost portion of the lining in the elevationally-elongated opening;
etching the ion-implanted elemental-form silicon of the uppermost portion of the lining selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting;
reacting the elemental-form silicon of the lower portion of the lining with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide; and
forming conductive material in the elevationally-elongated opening atop and directly against the elemental-form metal.
2. The method of claim 1 comprising forming the elemental-form silicon centrally over a bottom of the elevationally-elongated opening whereby the lining as initially formed is of an upwardly-open container shape.
3. The method of claim 1 comprising forming the lining radially-outside of the elevationally-elongated opening over a top surface of material in which the elevationally-elongated opening is received, the ion implanting occurring into the elemental-form silicon of that portion of the lining that is radially-outside of the elevationally-elongated opening, said etching removing the elemental-form silicon of that portion of the lining that is radially-outside of the elevationally-elongated opening.
4. The method of claim 1 wherein the ion implanting is at an angle from vertical such that none of the elemental-form silicon of the lower portion is subjected to said ion implanting.
5. The method of claim 1 wherein the ion implanting is vertical.
6. The method of claim 5 comprising:
forming the elemental-form silicon centrally over a bottom of the elevationally-elongated opening whereby the lining is of an upwardly-open container shape having a container bottom received radially-inward of container sidewalls, the container bottom comprising the elemental-form silicon;
the vertical ion implanting also being into the elemental-form silicon of the container bottom of the lower portion of the lining; and
the ion-implanted container bottom being etched away when etching the ion-implanted elemental-form silicon of the uppermost portion of the lining.
7. The method of claim 1 wherein the substance is at least one of As, Ge, Ar, In, Sb, and BF 2 .
8. The method of claim 1 wherein the etching comprises use of H 3 PO 4 .
9. The method of claim 1 wherein the metal halide is at least one of a fluoride and a chloride.
10. The method of claim 1 wherein the elemental-form metal is at least one of W, Mo, Nb, Ni, Co, and Ta.
11. The method of claim 1 wherein the metal halide comprises WF 6 and the elemental-form metal is W.
12. The method of claim 1 wherein the conductive material comprises metal material that is directly against the elemental-form metal.
13. The method of claim 12 wherein the metal material is the elemental-form metal.
14. The method of claim 13 wherein the elemental-form metal in the lower portion of the elevationally-elongated opening and the elemental-form metal of the conductive material are crystalline and of different crystalline phases relative one another.
15. The method of claim 1 wherein the lining after the reacting comprises a metal silicide radially-outward and directly against the elemental-form metal, the metal of the metal silicide being the metal from the metal halide.
16. The method of claim 1 wherein the lining comprises metal material radially-outward of the elemental-form silicon.
17. The method of claim 16 wherein the lining comprises insulator material radially-outward of the metal material.
18. The method of claim 17 wherein the lining after the reacting comprises a metal silicide sandwiched radially-between the metal material and the elemental-form metal, the metal of the metal silicide being the metal from the metal halide.
19. The method of claim 1 wherein the elemental-form silicon is polycrystalline.
20. The method of claim 1 wherein the elemental-form silicon is monocrystalline.
21. The method of claim 1 wherein the elemental-form silicon is amorphous.
22. The method of claim 1 comprising:
forming a memory array comprising strings of memory cells including forming a stack comprising vertically-alternating insulative tiers and conductive tiers, the memory-cell strings comprising channel-material strings in the stack; and forming the elevationally-elongated opening at least partially through the stack.
23. The method of claim 22 comprising forming the elevationally-elongated opening through the stack, the conductive via comprising a through-array-via.
24. The method of claim 22 comprising NAND.
25. A method used in forming a conductive via of integrated circuitry, comprising:
forming a lining laterally over sidewalls of an elevationally-elongated opening, the lining comprising elemental-form silicon;
vertically recessing the elemental-form silicon of an uppermost portion of the lining in the elevationally-elongated opening relative to the elemental-form silicon of a lower portion of the lining that is below the uppermost portion;
reacting the elemental-form silicon of the lower portion of the lining with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide; and
forming conductive material in the elevationally-elongated opening atop and directly against the elemental-form metal.
26. The method of claim 25 wherein the vertical recessing comprises timed non-selective etching of the elemental-form silicon of the uppermost portion of the lining relative to the elemental-form silicon of the lower portion of the lining.
27. The method of claim 26 wherein the elemental-form silicon of the uppermost portion and the lower portion of the lining are of the same composition relative one another.
28. The method of claim 25 wherein the elemental-form silicon of the uppermost portion and the elemental-form silicon of the lower portion of the lining are of different compositions relative one another, the vertical recessing comprising etching the elemental-form silicon of the uppermost portion of the lining selectively relative to the elemental-form silicon of the lower portion of the lining.
29. The method of claim 28 wherein the different compositions result from changing deposition conditions during a deposition of the elemental-form silicon of the uppermost portion of the lining.
30. The method of claim 28 wherein the different compositions result from changing composition of the elemental-form silicon of the uppermost portion of the lining after it has been formed.