IP Library Granted Patent US 11,757,412
Granted Patent B2
US 11,757,412 · App. 16/989,958 · Granted Sep 12, 2023

Control of envelope tracker PMIC

Inventors: Ilan Sutskover (Hadera M, IL); Eran Segev (Tel Aviv TA, IL); Stephan Henzler (Munich, DE); Alexander Belitzer (Munich, DE)
Assignee: Intel Corporation
H03F1/0222H03F1/025H03F1/34H03F3/195H03F3/24H03F3/245H04W76/27H03F3/189H03F2200/102H03F2200/504H03F2200/507H03F2200/511H03F2200/546H03K23/005
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Quick Facts
Patent No.
US 11,757,412
App. No.
16/989,958
Granted
Sep 12, 2023
Kind
B2
Abstract

A tracker circuit configured to provide a variable supply voltage to a power amplifier (PA) circuit is disclosed. The tracker circuit includes a state machine circuit comprising a plurality of states mapped in accordance with transitions associated with a mapping scheme. In some embodiments, the plurality of states of the state machine circuit identify one or more operational modes associated with the tracker circuit, wherein at least one operational mode comprises one or more voltage levels respectively associated therewith. In some embodiments, the one or more operational modes includes at least two active operational modes. In some embodiments, a transition between the one or more operational modes of the tracker circuit is controlled by a digital selection signal received from a digital communication interface associated therewith.

Claims (26)

1. A tracker circuit configured to provide a variable supply voltage to a power amplifier (PA) circuit comprising:

a state machine circuit comprising a plurality of states, wherein the plurality of states of the state machine circuit identify operational modes associated with the tracker circuit, wherein each operational mode comprises one or more voltage levels respectively associated therewith; and

wherein a transition between the operational modes of the tracker circuit is controlled by a digital selection signal received from a digital communication interface,

wherein the plurality of states of the state machine circuit are mapped in accordance with a transition between the operational modes of the tracker circuit.

2. The tracker circuit of claim 1 , wherein the plurality of states of the state machine circuit are mapped in accordance with a mapping scheme and a transition between the operational modes of the tracker circuit is defined based on mapping the operational modes to trajectories comprising state transitions associated with the mapping scheme.

3. The tracker circuit of claim 2 , wherein the states of the state machine circuit are mapped by utilizing allowable transitions associated with Gray mapping.

4. The tracker circuit of claim 2 , wherein the states of the state machine circuit are mapped by utilizing allowable transitions and forbidden transitions associated with Gray mapping.

5. The tracker circuit of claim 4 , wherein the forbidden transition is used to indicate a transition between the operational modes.

6. The tracker circuit of claim 1 , wherein the plurality of states are divided into multiple subsets of states and each subset of states is associated with a different operational mode.

7. The tracker circuit of claim 1 , wherein the plurality of states of the state machine circuit further identify at least one inactive operational mode.

8. The tracker circuit of claim 7 , wherein the at least one inactive operational mode comprises one or more of an off mode, a standby mode and an idle mode.

9. The tracker circuit of claim 1 , wherein the operational modes comprise an envelope tracking (ET) mode.

10. The tracker circuit of claim 1 , wherein the operational modes comprise an average power tracking (APT) mode.

11. The tracker circuit of claim 1 , wherein the operational modes comprise a non-tracking mode.

12. An envelope tracking system, comprising:

a tracker circuit configured to provide a variable supply voltage to a power amplifier (PA) circuit, wherein the tracker circuit comprises a state machine circuit comprising a plurality of states, wherein the plurality of states of the state machine circuit identify operational modes associated with the tracker circuit, wherein each operational mode comprises one or more voltage levels respectively associated therewith and wherein a transition between the operational modes of the tracker circuit is controlled by a digital selection signal received from a digital communication interface; and

a level selector circuit configured to generate the digital selection signal based on a measurement of a parameter associated with the PA circuit,

wherein the plurality of states of the state machine circuit are mapped in accordance with a transition between the operational modes of the tracker circuit.

13. The envelope tracking system of claim 12 , wherein a transition between the operational modes of the tracker circuit is defined based on mapping the operational modes to trajectories comprising state transitions associated with a mapping scheme.

14. The envelope tracking system of claim 13 , wherein the states of the state machine circuit are mapped by utilizing allowable transitions associated with Gray mapping.

15. The envelope tracking system of claim 13 , wherein the states of the state machine circuit are mapped by utilizing allowable transitions and forbidden transitions associated with Gray mapping.

16. The envelope tracking system of claim 15 , wherein the forbidden transition is used to indicate a transition between the operational modes.

17. The envelope tracking system of claim 12 , wherein the plurality of states are divided into multiple subsets of states and each subset of states is associated with a different operational mode.

18. The envelope tracking system of claim 12 , wherein the operational modes comprise one or more of an off mode, a standby mode and an idle mode.

19. The envelope tracking system of claim 12 , wherein the operational modes comprise an envelope tracking (ET) mode.

20. The envelope tracking system of claim 12 , wherein the operational modes comprise an average power tracking (APT) mode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056323/0278 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2020
From: HENZLER, STEPHAN; BELITZER, ALEXANDER; SUTSKOVER, ILAN; SEGEV, ERAN
To: INTEL IP CORPORATION
Reel/Frame 053609/0864 →
Continuity (3)
Continuation 16387986 · Apr 18, 2019
Continuation 15866951 · Jan 10, 2018
Related Publication 20210058036A1 · Feb 25, 2021
Cited By (1)
US 12,489,408