Instruction length based parallel instruction demarcator

1. An instruction demarcator comprising:

an instruction buffer to receive and store an instruction sequence comprising a plurality of instruction syllables;

two or more logic blocks arranged in a sequence of a plurality of stages that individually receive respective sets of one or more field positioned bits of respective individual ones of the plurality of instruction syllables from the instruction buffer as respective first inputs, the two or more logic blocks generating respective LENCARRY signals,

wherein individual ones of the two or more logic blocks receive respective second inputs coupled to the respective LENCARRY signals from respective preceding stages of the plurality of stages,

wherein the two or more logic blocks are configured to determine a length of at least one instruction and at least one boundary, and wherein the respective LENCARRY signals are used to indicate a last syllable of the at least one instruction; and

a controlling logic block to demarcate the instruction sequence into individual instructions at the at least one boundary based on the respective LENCARRY signals.

2. The instruction demarcator of claim 1 , wherein the two or more logic blocks are configured to individually generate one or more control signals, and wherein the one or more control signals comprise one or more members selected from the group consisting of: a single syllable instruction signal, a multi-syllable instruction signal, an incomplete instruction carryover signal, and an end of instruction marker.

3. The instruction demarcator of claim 1 , wherein the respective sets of one or more field positioned bits of respective individual instruction syllables are used to determine the length of the at least one instruction.

4. The instruction demarcator of claim 1 , wherein an instruction syllable of the plurality of instruction syllables is a single syllable instruction.

5. The instruction demarcator of claim 1 , wherein two or more instruction syllables of the plurality of instruction syllables are a multi-syllable instruction.

6. The instruction demarcator of claim 1 , wherein the two or more logic blocks are configured such that respective last syllables are identified at ends of respective individual instructions.

7. The instruction demarcator of claim 1 , wherein the controlling logic block generates output signals that are based on the respective LENCARRY signals generated by the two or more logic blocks, the output signals configured to control a data bus.

8. The instruction demarcator of claim 7 , wherein the output signals transmit tag values.

9. The instruction demarcator of claim 7 , wherein the output signals transmit a start-of-instruction flag with an instruction syllable.

10. The instruction demarcator of claim 1 , wherein the instruction demarcator further comprises one or more instruction queues to receive and store at least one of a single syllable instruction of the plurality of instruction syllables or a multi-syllable instruction of the plurality of instruction syllables within the one or more instruction queues.

11. The instruction demarcator of claim 1 , wherein the instruction demarcator further comprises one or more instruction decoders to decode the individual instructions after demarcation.

12. The instruction demarcator of claim 1 , wherein the controlling logic block is configured such that a sequence of two or more decoupler control signals is generated, arranged in correspondence with the two or more logic blocks arranged in a sequence of a plurality of stages.

13. The instruction demarcator of claim 12 , wherein respective individual ones of the two or more decoupler control signals are input to respective individual ones of the two or more logic blocks arranged in a sequence.

14. The instruction demarcator of claim 13 , wherein at least one of the two or more logic blocks is configured to be decoupled from one of the respective second inputs based on the respective individual ones of the two or more decoupler control signals.

15. The instruction demarcator of claim 12 , wherein the controlling logic block is configured such that a target address is received as input by the controlling logic block to configure the two or more decoupler control signals, and wherein the target address includes a target equivalent address which identifies a target instruction syllable of the plurality of instruction syllables corresponding with a next starting point.

16. The instruction demarcator of claim 15 , wherein the target address is generated in response to redirection of an execution thread.

17. The instruction demarcator of claim 1 , wherein the controlling logic block comprises at least two multiplexers to demarcate and output individual instructions.

18. The instruction demarcator of claim 1 , wherein the two or more logic blocks are configured to individually generate a size indicator signal.

19. A method to demarcate instructions comprising:

receiving and storing an instruction sequence comprising a plurality of instruction syllables in an instruction buffer;

configuring two or more logic blocks arranged in a sequence of a plurality of stages to individually receive respective sets of one or more field positioned bits of respective individual ones of the plurality of instruction syllables from the instruction buffer as respective first inputs, wherein the two or more logic blocks generate respective LENCARRY signals,

wherein individual ones of the two or more logic blocks receive respective second inputs coupled to the respective LENCARRY signals from respective preceding stages of the plurality of stages, wherein the two or more logic blocks determine a length of at least one instruction and at least one boundary, and wherein the respective LENCARRY signals are used to indicate a last syllable of the at least one instruction; and

configuring a controlling logic block to demarcate the instruction sequence into individual instructions at the at least one boundary based on the respective LENCARRY signals.