IP Library › Assignment 075401/0645
Patent Assignment
Reel/Frame 075401/0645

Assignment of Assignor's Interest

Recorded: 2026-07-26 Pages: 5
Assignor
YADAVALLI, SITARAM, DR.
Executed: 2026-07-18
Assignee
ONNIVATION LLC
1529 MONTELLANO DR, SAN JOSE, CALIFORNIA, 95120
Covered Properties (22)
Virtual Memory Paging System and Translation Lookaside Buffer with Pagelets
Application: 19/447,797 →
Publication: US US20260211820A1
Computing Machine with Secure Matrix Space of Row and Column Major Access Memory
Application: 18/952,950 →
Publication: US US20250165252A1
Instruction Operand Prefixing Combinator and Decoder for Extensibility and Backward Compatibility
Application: 18/662,639 →
Publication: US US20250306938A1
Parallel Instruction Demarcator
Application: 18/648,259 →
Publication: US US20240281251A1
Instruction Operand Prefixing Combinator and Decoder for Extensibility and Backward Compatibility
Application: 18/433,384 →
Publication: US US20240281707A1
Computing Machine Using a Matrix Space And Matrix Pointer Registers For Matrix and Array Processing
Application: 18/239,031 →
Publication: US US20240004655A1
Hardware and Methods for Extending Length of Immediate Operands in Machine Instructions
Application: 18/219,575 →
Publication: US US20240004654A1
Instruction Operand Prefixing Combinator and Decoder for Extensibility and Backward Compatibility
Application: 63/444,318 →
Virtual Memory Paging and Translation Lookaside Buffer with Pagelets
Application: 63/349,453 →
Instruction Demarcator
Application: 62/931,435 →
Computing Machine Architecture for Matrix and Array Processing
Application: 15/488,494 →
Publication: US US20170337156A1
Method and Apparatus for Storing and Accessing Matrices and Arrays by Columns and Rows in a Processing Unit
Application: 62/338,418 →
Computing Machine Architecture for Matrix and Array Processing
Application: 62/327,949 →
Virtual Memory Paging System and Translation Lookaside Buffer with Pagelets
Application: 18/692,192 →
Publication: US US20250094356A1
Computing Machine with Secure Matrix Space
Application: 18/406,184 →
Publication: US US20240160444A1
Secure Matrix Space with Partitions for Concurrent Use
Application: 17/553,600 →
Publication: US US20220156066A1
Parallel Instruction Demarcator
Application: 17/526,882 →
Publication: US US20220137971A1
Instruction Length Based Parallel Instruction Demarcator
Application: 16/991,408 →
Publication: US US20200387375A1
Secure Matrix Space with Partitions for Concurrent Use
Application: 16/783,125 →
Publication: US US20200174787A1
A Computing Machine Using a Matrix Space And Matrix Pointer Registers For Matrix and Array Processing
Application: 16/396,680 →
Publication: US US20190250915A1
Method and Apparatus for Storing and Accessing Matrices and Arrays by Columns and Rows in a Processing Unit
Application: 15/598,322 →
Publication: US US20190295631A1
Virtual Memory Paging System and Translation Lookaside Buffer with Pagelets