VIRTUAL MEMORY PAGING SYSTEM AND TRANSLATION LOOKASIDE BUFFER WITH PAGELETS
A page in a memory is sectioned into a plurality of pagelets of sizes smaller than the page thus speeding up data transfers. The pagelets in the page are used to store, transport and process data, wherein individual pagelets are transferred between-a memory and secondary storage in any order such that there is a reduction in the effective latency of the transfer of critical chunks of data. A pagelet translation lookaside buffer that handles translations for pages of different sizes and/or pages having pagelets is used to cache frequently used translations. A critical pagelet determiner is used to indicate the critical pagelet involved in a transaction. Pagelets of a page share one entry in a page table that also includes a virtual to physical translation. Pagelet validity and dirty indicators are maintained to determine pagelet eviction, writeback and fetch actions in accordance with pagelet handling policies.
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26 . A method to evict and write back a page that comprises a dirty pagelet to a secondary storage in a computing system, the method comprising:
presenting a virtual address of the page and probing a translation lookaside buffer that handles pages with pagelets, to find a matching translation entry;
presenting the virtual address of the page and reading one or more page tables to get an associated page table entry, the associated page table entry comprising pagelet states;
upon finding the matching translation entry, updating the pagelet states in the associated page table entry and invalidating the matching translation entry in the translation lookaside buffer;
checking pagelet states, and in response to finding the dirty pagelet, computing a physical address of the dirty pagelet, and a secondary storage address of the dirty pagelet; and
setting up a direct memory access transaction to transfer the dirty pagelet to the secondary storage and starting the direct memory access transaction.
27 . A method to insert a translation in a pagelet translation lookaside buffer in a system on a chip in a computing system, the method comprising:
presenting a virtual page number of a page to insert and reading one or more page tables to get an associated page table entry comprising a physical page number, pagelet states and page attributes;
probing the pagelet translation lookaside buffer that handles pages having pagelets to find a matching translation entry;
in response to finding the matching translation entry, updating the matching translation entry;
when no matching translation entry is found, then finding a replacement candidate entry in the pagelet translation lookaside buffer, and updating pagelet states of a corresponding page table entry in the one or more page tables, the corresponding page table entry associated with the replacement candidate entry;
creating a new translation comprising the virtual page number, an associated access control identifier, the physical page number, the pagelet states, and the page attributes; and
writing the new translation into the replacement candidate entry in the pagelet translation lookaside buffer.
28 . A translation lookaside buffer with support for handling pagelets in a computing system comprising:
a content addressable memory that holds at least one translation of a page, the page having pagelets;
a content matching port coupled to the content addressable memory, wherein a transaction comprising a virtual address is presented at the content matching port, and wherein in response to the transaction a matching translation is generated;
a critical pagelet determiner circuit that in response to the transaction determines a critical pagelet number of a critical pagelet, wherein the critical pagelet contains the location associated with the virtual address; and
a physical address computation logic circuit that in response to the critical pagelet number generates a physical address.
29 . The translation lookaside buffer of claim 28 , wherein the at least one translation comprises a type field to identify any page having pagelets.
30 . The translation lookaside buffer of claim 28 , wherein the at least one translation comprises a lock attribute, wherein asserting the lock attribute locks the page in a memory and prevents eviction of the page.
31 . The translation lookaside buffer of claim 28 , wherein the at least one translation comprises a lock attribute, and wherein the lock attribute when asserted prevents the at least one translation from replacement.
32 . The translation lookaside buffer of claim 28 , wherein the at least one translation comprises a permission field, wherein the permission field is used to mark the page as read-only, and/or used to mark the page as shared, or alternately, to allow reading and/or writing of the page.
33 . The translation lookaside buffer of claim 28 , wherein the at least one translation comprises a protection field that controls access restrictions.
34 . The translation lookaside buffer of claim 28 , wherein the at least one translation comprises a mask field or a size field to compute the address of a pagelet.
35 . The translation lookaside buffer of claim 28 , wherein the at least one translation comprises at least one access attribute that controls the access-type of the page.
36 . The translation lookaside buffer of claim 28 , wherein the at least one translation comprises pagelet validity indicators.
37 . The translation lookaside buffer of claim 28 , wherein the at least one translation comprises pagelet dirty indicators.
38 . The translation lookaside buffer of claim 28 , wherein the critical pagelet is transferred first in a transfer of the page having pagelets prior to transferring pagelets that are not identified as critical.
39 . The translation lookaside buffer of claim 28 , further comprising an exception generator that asserts an exception in response to the indication of a no matching translation entry.
40 . The translation lookaside buffer of claim 28 , further comprising a pagelet state and protection checker circuit.
41 . The translation lookaside buffer of claim 40 , wherein the pagelet state and protection checker circuit checks whether or not the transaction is allowed to access the addressed memory location.
42 . The translation lookaside buffer of claim 41 , further comprising an exception generator that generates an exception when the transaction is not allowed to access the addressed memory location or when the critical pagelet state is invalid.
43 . The translation lookaside buffer of claim 28 , wherein the at least one translation comprises at least one access control identifier.
44 . The translation lookaside buffer of claim 43 , wherein the access control identifier is an operating system identifier or an address space identifier or a process identifier.
45 . The method of claim 26 , further comprising returning a message in response to completion of the direct memory access transaction.