INSTRUCTION OPERAND PREFIXING COMBINATOR AND DECODER FOR EXTENSIBILITY AND BACKWARD COMPATIBILITY
Operand augmenting instruction combinators, decoders, and techniques for augmenting instruction operands to existing instructions to create new combined versions of the instructions that are executed. Hardware, computer program products and methods use mechanisms and/or techniques that comprise replacements, substitutions, embeddings, modifications, and/or combinations to include additional source, destination or other operands into instructions by combining them into the existing instructions. Variations in techniques facilitate combining existing instructions with multi-operand prefixes including a condition prefix to convert the existing instructions into conditional execution instructions. instructions can also be augmented with a function, and/or a type and/or a hint to modify the instructions' functionality to handle a wider class of operand types or classes of data, that improve execution speeds, as well as improving instruction set extensibility while maintaining backward compatibility. Instruction extension capability facilitates rapid repurposing of highly used matrix and machine learning related instructions for deep learning models and algorithms.
1 . A computing machine, comprising:
at least one processor in communication with a non-transitory memory, wherein the at least one processor executes instructions of the computing machine, the instructions of the computing machine comprising a first instruction and a second instruction, wherein the first instruction is an operand prefix instruction comprising at least one prefix operand;
an operand prefix identifying mechanism that identifies the operand prefix instruction and determines the at least one prefix operand; and
an operand selection mechanism that selects the at least one prefix operand and combines the at least one prefix operand with at least some portion of the second instruction to create a combined instruction.
2 . The computing machine of claim 1 , wherein the operand prefix identifying mechanism is a prefix instruction identifying pre-decoder.
3 . (canceled)
4 . The computing machine of claim 1 , wherein the operand prefix identifying mechanism is implemented in hardware.
5 . (canceled)
6 . The computing machine of claim 1 , wherein the at least one prefix operand serves as a destination operand of the combined instruction.
7 . The computing machine of claim 1 , wherein the at least one prefix operand serves as a source operand of the combined instruction.
8 . The computing machine of claim 1 , where in the at least one prefix operand is a register operand.
9 - 18 . (canceled)
19 . A computing machine comprising a pre-decoder that identifies an operand prefix instruction;
an operand analyzer that performs analysis and rejects or accepts at least one prefix operand to combine with a consuming instruction;
and an operand combiner that combines the at least one prefix operand with the consuming instruction to create a combined instruction for execution.
20 . The computing machine of claim 19 , wherein the operand prefix instruction is a register operand prefix instruction.
21 . The computing machine of claim 19 , wherein the operand prefix instruction is an extended register operand prefix instruction.
22 . The computing machine of claim 19 , wherein the operand prefix instruction comprises a new destination operand.
23 . The computing machine of claim 19 , wherein the operand prefix instruction is a condition operand prefix instruction.
24 . The computing machine of claim 19 , wherein the operand prefix instruction is a hint operand prefix instruction.
25 . The computing machine of claim 19 , wherein the operand prefix instruction is a type operand prefix instruction.
26 . The computing machine of claim 19 , wherein the operand prefix instruction is a function operand prefix instruction.
27 . A computing machine comprising an operand prefixing instruction combinator and decoder further comprising:
a first pre-decoder, wherein the first pre-decoder identifies an operand prefix instruction;
a second pre-decoder, wherein the second pre-decoder identifies a consuming instruction;
at least one operand analyzer that performs analysis and rejects or accepts at least one prefix operand to combine with the consuming instruction; and
at least one operand combiner that combines the at least one prefix operand with the consuming instruction to create a combined instruction.
28 . The computing machine of claim 27 , wherein the operand prefixing instruction combinator and decoder are multi-operand prefixing instruction combinator and decoder.
29 . The computing machine of claim 27 , wherein an operand prefix instruction comprises a condition operand and a destination operand.
30 . The computing machine of claim 27 , wherein the operand prefixing instruction combinator and decoder are implemented as a logic circuit.
31 . The computing machine of claim 27 , wherein the operand prefixing instruction combinator and decoder are implemented in microcode at least in part.
32 . The computing machine of claim 27 , wherein the computing machine comprises at least one processor that is in communication with a non-transitory memory, wherein the at least one processor executes instructions of the computing machine, wherein the operand prefixing instruction combinator is implemented in a software program product at least in part.