Integrated circuit devices and methods of manufacturing the same

1. An integrated circuit device comprising:

a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material;

an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner;

a capping layer surrounding an upper surface and an upper portion of the sidewall of the fin-type active area, including a second semiconductor material that is different from the first semiconductor material, wherein the capping layer comprises an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall, the facet surface inclined at a first angle with respect to the upper surface of the substrate, and the first angle is between about 30° to about 60°; and

a gate structure arranged on the capping layer and extending in a second direction that is parallel to the upper surface of the substrate and perpendicular to the first direction,

wherein the capping layer has a first thickness on the upper surface of the fin-type active area, wherein the capping layer has a second thickness along the sidewall of the fin-type active area, and wherein the second thickness is less than the first thickness, and

wherein a connection portion between the upper surface of the fin-type active area and the sidewall of the fin-type active area is rounded, and a profile of the connection portion is different from a profile of the faceted surface.

2. The integrated circuit device of claim 1 , wherein an upper surface of the insulation liner contacts a bottom surface of the capping layer, and

wherein the bottom surface of the capping layer is equidistant from the upper surface of the substrate as an upper surface of the isolation layer.

3. The integrated circuit device of claim 1 , wherein the fin-type active area includes silicon germanium, and wherein the capping layer includes silicon.

4. The integrated circuit device of claim 1 , wherein the fin-type active area includes a surface area having a distance that is less than a first distance from the sidewall of the fin-type active area, and an inside area having a distance that is greater than the first distance from the sidewall of the fin-type active area, and

wherein the surface area has a first germanium content and the inside area has a second germanium content that is less than the first germanium content.

5. The integrated circuit device of claim 4 ,

wherein the surface area of the fin-type active area has a first bandgap energy,

wherein the inside area of the fin-type active area has a second bandgap energy,

wherein the capping layer has a third bandgap energy, and

wherein the third bandgap energy is greater than the second bandgap energy and the second bandgap energy is greater than the first bandgap energy.

6. The integrated circuit device of claim 1 , further comprising:

an interface layer arranged between the capping layer and the gate structure, and

the interface layer includes the second semiconductor material including nitrogen at a first concentration.

7. An integrated circuit device comprising:

a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including silicon germanium;

an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner;

a capping layer surrounding an upper surface and the sidewall of the fin-type active area, the capping layer including silicon, and the capping layer comprising an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and

a gate structure arranged on the capping layer and extending in a second direction that is parallel to the upper surface of the substrate and perpendicular to the first direction,

wherein, on the sidewall of the fin-type active area, a bottom surface of the capping layer contacts an upper surface of the insulation liner,

wherein the fin-type active area includes a surface area having a distance that is less than a first distance from the sidewall of the fin-type active area, and an inside area having a distance that is greater than the first distance from the sidewall of the fin-type active area, and

wherein the surface area has a first germanium content and the inside area has a second germanium content that is less than the first germanium content.

8. The integrated circuit device of claim 7 , wherein an upper portion of the sidewall of the fin-type active area contacts the capping layer, and

the lower portion of the sidewall of the fin-type active area contacts the insulation liner.

9. The integrated circuit device of claim 7 , wherein the facet surface is inclined at a first angle between about 30° to about 60° with respect to the upper surface of the substrate,

wherein the capping layer has a first thickness on the upper surface of the fin-type active area, and

wherein the capping layer has a second thickness at an edge of the facet surface, the second thickness being less than the first thickness.

10. An integrated circuit device comprising:

a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material;

an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area;

a capping layer surrounding an upper surface and the sidewall of the fin-type active area, the capping layer including a second semiconductor material that is different from the first semiconductor material, wherein the capping layer comprises an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall, wherein the capping layer has a first thickness on the upper surface of the fin-type active area, wherein the capping layer has a second thickness along a side surface of the fin-type active area, and wherein the second thickness is less than the first thickness; and

a gate structure arranged on the capping layer and extending in a second direction that is parallel to the upper surface of the substrate and perpendicular to the first direction.

11. The integrated circuit device of claim 10 , wherein the isolation layer includes an insulation liner arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner.

12. The integrated circuit device of claim 10 , wherein the facet surface is inclined at a first angle with respect to the upper surface of the substrate, and the first angle is between about 30° to about 60°.

13. The integrated circuit device of claim 10 , wherein an upper surface of the isolation layer contacts a bottom surface of the capping layer, and wherein the bottom surface of the capping layer is as far from the upper surface of the substrate as an upper surface of the isolation layer is from the upper surface of the substrate.

14. The integrated circuit device of claim 10 , wherein the fin-type active area includes silicon germanium, and wherein the capping layer includes silicon.

15. The integrated circuit device of claim 10 , wherein the fin-type active area includes a surface area having a distance that is less than a first distance from the sidewall of the fin-type active area, and an inside area having a distance that is greater than the first distance from the sidewall of the fin-type active area, and

wherein the surface area has a first germanium content and the inside area has a second germanium content that is less than the first germanium content.

16. The integrated circuit device of claim 15 , wherein the surface area of the fin-type active area has a first bandgap energy, wherein the inside area of the fin-type active area has a second bandgap energy, wherein the capping layer has a third bandgap energy, and wherein the third bandgap energy is greater than the second bandgap energy and the second bandgap energy is greater than the first bandgap energy.