High bandwidth die to die interconnect with package area reduction

1. A package structure comprising:

a first wiring layer including a first side and a second side opposite the first side;

a first die and a vertical interposer side-by-side on the first side of the first wiring layer, wherein the vertical interposer includes electrical interconnects from a first side of the vertical interposer coupled with the first side of the first wiring layer to a second side of the vertical interposer opposite the first side of the vertical interposer;

a second die face down on and electrically connected with the second side of the vertical interposer; and

a local interposer on the second side of the first wiring layer and in electrical connection with the first die and the vertical interposer, wherein the local interposer is completely underneath a footprint of the second die;

wherein the second die includes a first lateral die edge and a second lateral die edge opposite the first lateral die edge and a plurality of terminals that is offset toward the first lateral die edge, wherein the plurality of terminals is electrically connected with the vertical interposer and the second lateral die edge of the second die spans over the first die.

2. The package of claim 1 , wherein the first die comprises a first core selected from the group consisting of a central processing unit and a graphics processing unit.

3. The package structure of claim 1 , wherein the first die and the second die comprise split logic.

4. The package structure of claim 1 , wherein the local interposer includes a plurality of terminals on a first side of the local interposer that is coupled with the second side of the first wiring layer, and the local interposer does not include a terminal on a second side of the local interposer opposite the first side of the local interposer.

5. The package structure of claim 1 , further comprising a first molding compound encapsulating the first die, the vertical interposer, and the second die.

6. The package structure of claim 1 , wherein the first die occupies a larger area than the second die.

7. The package structure of claim 1 , further comprising a mechanical chiplet attached to the first die laterally adjacent to the second die.

8. The package structure of claim 1 , wherein the local interposer overlaps the first die and the vertical interposer.

9. The package structure of claim 1 , wherein the first die includes first transistors of a first size, and the second die includes second transistors of a second size different than the first size.

10. The package of claim 2 , wherein the second die comprises a memory core.

11. The package of claim 2 , wherein the second die comprises an RF core.

12. The package structure of claim 5 , further comprising a second molding compound encapsulating the local interposer on the second side of the first wiring layer.

13. The package structure of claim 12 , further comprising a first plurality of conductive pillars extending from the first wiring layer and through the first molding compound.

14. The package structure of claim 13 , further comprising a second plurality of conductive pillars extending from the first wiring layer and through the second molding compound.

15. The package structure of claim 14 , further comprising a second wiring layer on the second molding compound and connected to the second plurality of conductive pillars.

16. The package structure of claim 15 , wherein the second wiring layer is on a planarized surface including the second molding compound, the second plurality of conductive pillars, and the local interposer.

17. The package structure of claim 6 , wherein the second die occupies a larger area than both the vertical interposer and the local interposer.

18. The package structure of claim 8 , wherein the second die completely overlaps the local interposer.