Fin structure for fin field effect transistor and method for fabrication the same

1. A fin structure for a fin field effect transistor, comprising:

a substrate, including a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view;

an isolation layer, disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed;

a stress buffer layer, disposed on sidewalls of the silicon fins between the isolation layer and the lower portion of the silicon fins, wherein the stress buffer layer is made up of a nitride portion and an amorphous silicon portion; and

an atomic layer deposition layer, disposed between the stress buffer layer and each of the silicon fins,

wherein a material of the nitride portion is silicon nitride,

wherein the nitride portion is a single layer,

wherein the amorphous silicon portion is disposed between the nitride portion and each of the silicon fins,

wherein the top of the silicon fins is exposed by the amorphous silicon portion.

2. The fin structure as recited in claim 1 , wherein the substrate includes a silicon wafer or a silicon on insulator (SOI) substrate.

3. The fin structure as recited in claim 1 , wherein the isolation layer includes a flowable chemical vapor deposition (FCVD) dielectric layer.

4. The fin structure as recited in claim 3 , wherein the FCVD dielectric layer includes flowable oxide.

5. The fin structure as recited in claim 1 , wherein the nitride portion of the stress buffer layer is a nitriding part of the stress buffer layer.