IP Library › Granted Patent US 11,588,023
Granted Patent B2
US 11,588,023 · App. 16/992,172 · Granted Feb 21, 2023

Semiconductor device, method for manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator

Inventor: Tatsuo Shimizu (Shinagawa, JP)
Assignee: KABUSHIKI KAISHA TOSHIBA
H01L29/1608H01L29/0878H01L29/41725H01L29/456
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Quick Facts
Patent No.
US 11,588,023
App. No.
16/992,172
Granted
Feb 21, 2023
Kind
B2
Abstract

A semiconductor device according to an embodiment includes: a silicon carbide layer; a metal layer; and a conductive layer positioned between the silicon carbide layer and the metal layer, the conductive layer containing a silicide of one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), and the conductive layer having a carbon concentration of 1×10 17 cm −3 or less.

Claims (33)

1. A semiconductor device comprising:

a silicon carbide layer;

a metal layer; and

a conductive layer positioned between the silicon carbide layer and the metal layer, a face of the conductive layer opposite to the metal layer being in contact with the silicon carbide layer, the conductive layer containing a silicide of one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), and the conductive layer having a carbon concentration of 1×10 17 cm −3 or less.

2. The semiconductor device according to claim 1 , wherein an atomic ratio (M/Si) of the metal element (M) to silicon (Si) in the conductive layer is 1.2 or more.

3. The semiconductor device according to claim 1 , wherein a carbon concentration of the metal layer is 1×10 17 cm −3 or less.

4. The semiconductor device according to claim 1 , wherein

the silicon carbide layer contains an impurity, the impurity being a p-type impurity or an n-type impurity, and

a concentration distribution of the impurity in the silicon carbide layer and the conductive layer has a peak at an interface between the silicon carbide layer and the conductive layer.

5. The semiconductor device according to claim 1 , wherein

the silicon carbide layer contains aluminum, and

the conductive layer has an aluminum concentration of 1×10 17 cm −3 or less.

6. The semiconductor device according to claim 1 , further comprising

an insulating layer in contact with the silicon carbide layer on a side of the silicon carbide layer where the metal layer is positioned,

wherein a depth of an interface between the silicon carbide layer and the conductive layer, when an interface between the silicon carbide layer and the insulating layer is set as a reference, is 50 nm or more.

7. An inverter circuit comprising the semiconductor device according to claim 1 .

8. A driving device comprising the semiconductor device according to claim 1 .

9. A vehicle comprising the semiconductor device according to claim 1 .

10. An elevator comprising the semiconductor device according to claim 1 .

11. A semiconductor device comprising:

a silicon carbide layer having a first plane and a second plane facing the first plane, the silicon carbide layer including a first silicon carbide region of n-type, a second silicon carbide region of p-type positioned between the first silicon carbide region and the first plane, a third silicon carbide region of n-type positioned between the second silicon carbide region and the first plane and having a n-type impurity concentration higher than a n-type impurity concentration of the first silicon carbide region, and a fourth silicon carbide region of p-type positioned between the first silicon carbide region and the first plane and having a p-type impurity concentration higher than a p-type impurity concentration of the second silicon carbide region;

a gate electrode positioned on a side of the first plane of the silicon carbide layer;

a gate insulating layer positioned between the gate electrode and the second silicon carbide region;

a first electrode positioned on the side of the first plane of the silicon carbide layer and electrically connected to the third silicon carbide region and the fourth silicon carbide region;

a second electrode positioned on a side of the second plane of the silicon carbide layer and electrically connected to the first silicon carbide region; and

a conductive layer positioned between the silicon carbide layer and the first electrode, a face of the conductive layer opposite to the metal layer being in contact with the fourth silicon carbide region, the conductive layer containing a silicide of one metal element (M) selected from a group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), and the conductive layer having a carbon concentration of 1×10 17 cm −3 or less.

12. The semiconductor device according to claim 11 , wherein an atomic ratio (M/Si) of the metal element (M) to silicon (Si) in the conductive layer is 1.2 or more.

13. The semiconductor device according to claim 11 , wherein a carbon concentration of the first electrode is 1×10 17 cm −3 or less.

14. The semiconductor device according to claim 11 , wherein

the fourth silicon carbide region contains aluminum, and

the conductive layer has an aluminum concentration of 1×10 17 cm −3 or less.

15. The semiconductor device according to claim 11 , wherein a depth of the conductive layer is deeper than a depth of the third silicon carbide region.

16. The semiconductor device according to claim 11 , wherein a thickness of the conductive layer in a direction from the first plane to the second plane is larger than 100 nm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2020
From: SHIMIZU, TATSUO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 054602/0316 →
Priority Claims (1)
JP JP2020-044566 · Mar 13, 2020 · national
Continuity (1)
Related Publication 20210288147A1 · Sep 16, 2021