IP Library › Granted Patent US 11,276,752
Granted Patent B2
US 11,276,752 · App. 16/995,054 · Granted Mar 15, 2022

Method for forming a device comprising a bipolar transistor

Inventors: Alexis Gauthier (Meylan, FR); Pascal Chevalier (Chapareillan, FR); Gregory Avenier (Saint Nazaire les Eymes, FR)
Assignee: STMicroelectronics (Crolles 2) SAS
H01L29/0642H01L29/66234H01L29/7322
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Quick Facts
Patent No.
US 11,276,752
App. No.
16/995,054
Granted
Mar 15, 2022
Kind
B2
Abstract

A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.

Claims (34)

1. A method for forming a device comprising a bipolar transistor, comprising:

forming an isolating trench in a semiconductor substrate;

implanting dopants to form a primary part of a collector region of the bipolar transistor buried in the semiconductor substrate below the isolating trench;

forming a first opening in the isolating trench which extends through the isolating trench to reach said semiconductor substrate;

implanting dopants through said first opening to form a secondary part of the collector region of the bipolar transistor extending over said primary part; and

epitaxially growing a base region of the bipolar transistor in the first opening and laterally surrounded by said isolating trench.

2. The method according to claim 1 , further comprising:

forming an emitter region of the bipolar transistor on the base region; and

forming an insulating spacer on each lateral surface surfaces of the emitter region.

3. The method according to claim 2 , wherein a width of each insulating spacer is greater than about 40 nm.

4. The method according to claim 2 , further comprising:

forming a stack of at least one isolating layer on the base region; and

forming a second opening in the stack;

wherein forming the emitter region comprises epitaxially growing said emitter region in the second opening.

5. The method according to claim 4 , further comprising removing the stack and wherein forming the insulating spacer comprises forming spacers on each lateral surface of the emitter region.

6. The method according to claim 5 , wherein a width of each spacer is greater than about 40 nm.

7. The method according to claim 1 , further comprising forming a deep trench isolation surrounding the bipolar transistor, said deep trench isolation having a depth in the semiconductor substrate which is greater than a depth of the isolating trench.

8. The method according to claim 1 , wherein said semiconductor substrate is made of a non-doped semiconductor material.

9. The method according to claim 8 , wherein portions of the non-doped semiconductor material laterally surround the secondary part of the collector.

10. A method for forming a device comprising a bipolar transistor, comprising:

forming an isolating trench in a semiconductor substrate;

implanting dopants to form a primary part of a collector region of the bipolar transistor buried in the semiconductor substrate below the isolating trench;

forming a first opening in the isolating trench which extends through the isolating trench to reach said semiconductor substrate;

epitaxially growing a base region of the bipolar transistor in the first opening and laterally surrounded by said isolating trench;

forming a stack of at least one isolating layer on the base region;

forming a second opening extending through the stack;

implanting dopants through said second opening to form a secondary part of the collector region of the bipolar transistor in the semiconductor substrate between said primary part and the base region; and

epitaxially growing an emitter region of the bipolar transistor in said second opening.

11. The method of claim 10 , further comprising removing the stack.

12. The method of claim 11 , further comprising forming an insulating spacer on each lateral surface of the emitter region.

13. The method of claim 12 , wherein a width of each insulating spacer is greater than about 40 nm.

14. The method of claim 10 , further comprising forming a deep trench isolation surrounding the bipolar transistor, said deep trench isolation having a depth in the semiconductor substrate which is greater than a depth of the isolating trench.

15. The method of claim 10 , wherein said semiconductor substrate is made of a non-doped semiconductor material.

16. The method according to claim 15 , wherein portions of the non-doped semiconductor material laterally surround the secondary part of the collector.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2020
From: GAUTHIER, ALEXIS; CHEVALIER, PASCAL; AVENIER, GREGORY
To: STMICROELECTRONICS (CROLLES 2) SAS
Reel/Frame 053512/0160 →
Priority Claims (1)
FR 1909282 · Aug 19, 2019 · national
Continuity (1)
Related Publication 20210057520A1 · Feb 25, 2021