Private memory management using utility thread

1. An apparatus, comprising:

graphics processor circuitry configured to:

generate a pool of private memory pages for a set of graphics work that includes multiple threads, prior to execution of the multiple threads;

maintain a translation table in memory, wherein the translation table is configured to map private memory addresses to virtual addresses based on identifiers of the threads;

execute a first thread to:

receive a request to allocate a private memory page for a second thread of the multiple threads, based on execution of a map request instruction by the second thread;

select a private memory page from the pool in response to the request; and

populate an entry in the translation table that maps the selected page for the second thread in response to the request; and

execute one or more instructions of the second thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table.

2. The apparatus of claim 1 , wherein the first thread is a persistent thread for which execution resources of the graphics processor circuitry are allocated for an entirety of a time interval over which the set of graphics work is executed.

3. The apparatus of claim 1 , wherein the graphics processor circuitry is further configured to:

translate the virtual address to a physical address of a location in a memory device.

4. The apparatus of claim 1 , wherein the second thread is configured to request to allocate a first number of private memory pages based on shader execution state information for the second thread, wherein the shader execution state information was received in information generated by a compiler prior to the execution.

5. The apparatus of claim 1 , wherein the graphics processor circuitry is further configured to:

determine a size for the pool of private memory pages based on shader execution state information that indicates private memory requirements of the multiple threads in the set of graphics work.

6. The apparatus of claim 1 , wherein the graphics processor circuitry is further configured to execute a map instruction of the first thread to map the selected page in response to an allocation request instruction executed by the second thread.

7. The apparatus of claim 6 , wherein the graphics processor circuitry is further configured to execute the first thread to load one or more page addresses into general purpose registers of the first thread and wherein the map instruction writes the page addresses to a translation table entry for the second thread.

8. The apparatus of claim 1 , wherein the graphics processor circuitry is further configured to execute multiple threads that include a utility program executable to modify the translation table and wherein the multiple threads use atomic operations to modify the translation table.

9. The apparatus of claim 1 , further comprising:

arbitration circuitry configured to select from among multiple threads requesting allocation of private memory from the first thread.

10. The apparatus of claim 1 , wherein the graphics processor circuitry is further configured to delay de-allocation of the private memory page until the end of a group of processing work and to allow one or more other threads to use the private memory page.

11. The apparatus of claim 1 , wherein the graphics processor circuitry is further configured to:

determine a number of threads to be preempted in response to a preemption request; and

allocate, based on the determination, a number of private memory pages to save preempted threads' state.

12. The apparatus of claim 1 , wherein the graphics processor circuitry is further configured to execute the first thread to:

allocate one or more additional unrequested private memory pages to reduce latency of one or more subsequent allocation requests.

13. The apparatus of claim 1 , wherein the apparatus is a computing device that includes:

an integrated circuit that includes the graphics processor circuitry; and

network interface circuitry.

14. The apparatus of claim 1 , wherein the identifiers of the threads are SIMD group identifiers and wherein the private memory space is interleaved based on a thread's position in its SIMD group.

15. A method, comprising:

generating a pool of private memory pages for a set of processing work that includes multiple threads, prior to execution of the multiple threads;

maintaining, by processor circuitry, a translation table in memory, wherein the translation table maps private memory addresses to virtual addresses based on identifiers of the threads;

executing, by the processor circuitry, a first thread to perform operations that include:

receiving a request to allocate a private memory page for a second thread of the multiple threads, based on execution of a map request instruction by the second thread;

selecting a private memory page from the pool in response to the request; and

populating an entry in the translation table that maps the selected page in the translation table for the second thread in response to the request; and

executing, by the processor, one or more instructions of the second thread to access a private memory space, wherein the executing includes translating a private memory address to a virtual address based on the mapped page in the translation table.

16. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:

graphics processor circuitry configured to:

generate a pool of private memory pages for a set of graphics work that includes multiple threads, prior to execution of the multiple threads;

maintain a translation table in memory, wherein the translation table is configured to map private memory addresses to virtual addresses based on identifiers of the threads;

execute a first thread to:

receive a request to allocate a private memory page for a second thread of the multiple threads, based on execution of a map request instruction by the second thread;

select a private memory page from the pool in response to the request; and

populate an entry in the translation table that maps the selected page for the second thread in response to the request; and

execute one or more instructions of the second thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table.

17. The non-transitory computer readable storage medium of claim 16 , wherein the graphics processor circuitry is further configured to:

translate the virtual address to a physical address of a location in a memory device.

18. The non-transitory computer readable storage medium of claim 16 , wherein the second thread is configured to request to allocate a first number of private memory pages based on shader execution state information for the second thread, wherein the shader execution state information was received from an external source prior to the execution.

19. The non-transitory computer readable storage medium of claim 16 , wherein the graphics processor circuitry is further configured to execute a map instruction of the first thread to map the selected page in response to an allocation request instruction executed by the second thread.

20. The non-transitory computer readable storage medium of claim 19 , wherein the graphics processor circuitry is further configured to execute the first thread to load one or more page addresses into general purpose registers of the first thread and wherein the map instruction writes the page addresses to a translation table entry for the second thread.