ESD structure and semiconductor structure
Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first semiconductor layers and the second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. Each of the first and second semiconductor layers has a first side contacting the first epitaxy region and a second side contacting the second epitaxy region, and the first side is opposite the second side.
1. An electrostatic discharge (ESD) structure, comprising:
a semiconductor substrate;
a first epitaxy region with a first type of conductivity over the semiconductor substrate;
a second epitaxy region with a second type of conductivity over the semiconductor substrate;
a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions;
at least one first conductive feature partially covering the first epitaxy region and the stacked first and second semiconductor layers; and
at least one second conductive feature partially covering the second epitaxy region and the stacked first and second semiconductor layers,
wherein each of the first and second semiconductor layers has a first side contacting the first epitaxy region and a second side contacting the second epitaxy region, and the first side is opposite the second side.
2. The ESD structure as claimed in claim 1 , wherein a first portion of the first conductive feature over the stacked first and second semiconductor layers is less than a second portion of the first conductive feature over the first epitaxy region, and a first portion of the second conductive feature over the stacked first and second semiconductor layers is less than a second portion of the second conductive feature over the second epitaxy region.
3. The ESD structure as claimed in claim 2 , wherein a distance between the first and second conductive features over the stacked first and second semiconductor layers is greater than a length of the first portion of the first and second conductive features over the stacked first and second semiconductor layers.
4. The ESD structure as claimed in claim 1 , wherein the first and second conductive features are formed within an oxide diffusion region.
5. The ESD structure as claimed in claim 1 , further comprising:
a third conductive feature formed over the first epitaxy region; and
a fourth conductive feature formed over the second epitaxy region.
6. The ESD structure as claimed in claim 5 , wherein the first epitaxy region has P-type conductivity and the second epitaxy region has N-type conductivity, and the third conductive feature is configured to couple a ground line to the first epitaxy region and the fourth conductive feature is configured to couple a power line to the second epitaxy region.
7. The ESD structure as claimed in claim 5 , wherein the first epitaxy region has N-type conductivity and the second epitaxy region has P-type conductivity, and the third conductive feature is configured to couple a power line to the first epitaxy region and the fourth conductive feature is configured to couple a ground line to the second epitaxy region.
8. The ESD structure as claimed in claim 1 , wherein the first and second conductive features are floating.
9. An electrostatic discharge (ESD) structure, comprising:
a semiconductor substrate;
a first epitaxy region with a first type of conductivity over the semiconductor substrate;
a second epitaxy region with a second type of conductivity over the semiconductor substrate; and
a plurality of Si layers and a plurality of SiGe layers alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions,
wherein each of the Si and SiGe layers has a first side contacting the first epitaxy region and a second side contacting the second epitaxy region, and the first side is opposite the second side,
wherein a first depth of the first and second epitaxy regions is greater than a second depth of the stacked Si and SiGe layers, so that an interface between the stacked Si and SiGe layers and the semiconductor substrate is higher than an interface between the first epitaxy region and the semiconductor substrate.
10. The ESD structure as claimed in claim 9 , further comprising:
at least one first conductive feature formed over the first epitaxy region and within an oxide diffusion region; and
at least one second conductive feature formed over the second epitaxy region and within the oxide diffusion region,
wherein the first and second conductive features extend along a first direction from the first epitaxy region to the second epitaxy region.
11. The ESD structure as claimed in claim 10 , wherein a width of the first conductive feature is less than a width of the oxide diffusion region along the first direction, and the width of the first conductive feature is equal to a width of the second conductive feature along the first direction.
12. The ESD structure as claimed in claim 9 , further comprising:
a third conductive feature formed over the first epitaxy region and within the oxide diffusion region; and
a fourth conductive feature formed over the second epitaxy region and within the oxide diffusion region.
13. The ESD structure as claimed in claim 12 wherein the first epitaxy region has P-type conductivity and the second epitaxy region has N-type conductivity, and the third conductive feature is configured to couple a ground line to the first epitaxy region and the fourth conductive feature is configured to couple a power line to the second epitaxy region.
14. The ESD structure as claimed in claim 12 , wherein the first epitaxy region has N-type conductivity and the second epitaxy region has P-type conductivity, and the third conductive feature is configured to couple a power line to the first epitaxy region and the fourth conductive feature is configured to couple a ground line to the second epitaxy region.
15. An electrostatic discharge (ESD) structure, comprising:
a semiconductor substrate;
a first epitaxy region with a first type of conductivity over the semiconductor substrate;
a second epitaxy region with a second type of conductivity over the semiconductor substrate; and
a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked in a junction region over the semiconductor substrate, wherein the first epitaxy region is separated from the second epitaxy region by the junction region,
wherein a first width of the first or second epitaxy region within an oxide diffusion (OD) region is greater than a second width of the junction region in a first direction from the first epitaxy region to the second epitaxy region,
wherein the first or second epitaxy regions have a third width in the first direction, and the third width is greater than the first width.
16. The ESD structure as claimed in claim 15 , further comprising:
at least one first conductive feature formed over the first epitaxy region and the junction region; and
at least one second conductive feature formed over the second epitaxy region and the junction region.
17. The ESD structure as claimed in claim 16 , wherein a first portion of the first conductive feature over the junction region is less than a second portion of the first conductive feature over the first epitaxy region, and a first portion of the second conductive feature over the junction region is less than a second portion of the second conductive feature over the second epitaxy region.
18. The ESD structure as claimed in claim 16 , wherein the first and second conductive features are formed within the OD region.
19. The ESD structure as claimed in claim 16 , further comprising:
a third conductive feature formed over the first epitaxy region; and
a fourth conductive feature formed over the second epitaxy region,
wherein the third and fourth conductive features are formed within the OD region.
20. The ESD structure as claimed in claim 19 , wherein the third and fourth conductive features are configured to couple different voltage lines to the first and second epitaxy regions.