IP Library Granted Patent US 11,069,414
Granted Patent B2
US 11,069,414 · App. 16/997,308 · Granted Jul 20, 2021

Non-volatile semiconductor storage device

Inventor: Naoki Matsunaga (Tokyo, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G11C16/26G06F3/064G06F3/0619G06F3/0655G06F3/0679G06F11/1068G11C11/5628G11C11/5642G11C16/04G11C16/0483G11C16/06G11C16/3404G11C16/349G11C16/3495G11C29/52
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Quick Facts
Patent No.
US 11,069,414
App. No.
16/997,308
Granted
Jul 20, 2021
Kind
B2
Abstract

According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Claims (35)

1. A memory system connectable to a host apparatus including a display device, the memory system comprising:

a nonvolatile memory; and

a controller circuit configured to:

receive a read request from the host apparatus;

on receiving the read request, perform a first read operation to read first data from the nonvolatile memory; and

if first error bits in the first data read by the first read operation are uncorrectable, send information about a life of the nonvolatile memory based on a number of the first error bits of uncorrectable to display the life of the nonvolatile memory on the display device.

2. The memory system according to claim 1 ,

wherein the information indicates that a number of the first error bits is greater than a threshold.

3. The memory system according to claim 1 ,

wherein the controller circuit is further configured, in response to the read request, to determine whether or not the first error bits in the first data read by the first read operation are uncorrectable.

4. The memory system according to claim 1 ,

wherein the controller circuit is configured to, if the first error bits in the first data read by the first read operation are uncorrectable, send information including a message indicating whether the life is nearing its end or not to display the message on the display device.

5. The memory system according to claim 3 ,

wherein the controller circuit is further configured to determine whether or not the number of the first error bits is greater than a threshold; and

wherein the controller circuit is configured to, if the first error bits is greater than the threshold, send information about the life of the nonvolatile memory to display the life of the nonvolatile memory on the display device.

6. The memory system according to claim 1 ,

wherein the nonvolatile semiconductor memory includes a plurality of memory cells, and each of the plurality of memory cells is configured to store two or more than two bits of data.

7. The memory system according to claim 1 ,

wherein the nonvolatile semiconductor memory is a NAND type flash memory.

8. A method of controlling a memory system connectable to a host apparatus including a display device, the memory system including a nonvolatile memory, the method comprising:

receiving a read request from the host apparatus;

on receiving the read request, performing a first read operation to read first data from the nonvolatile memory; and

if first error bits in the first data read by the first read operation are uncorrectable, sending information about a life of the nonvolatile memory based on a number of the first error bits of uncorrectable to display the life of the nonvolatile memory on the display device.

9. The method according to claim 8 ,

wherein the information indicates that a number of the first error bits is greater than a threshold.

10. The method according to claim 8 , further comprising

in response to the read request, determining whether or not the first error bits in the first data read by the first read operation are uncorrectable.

11. The method according to claim 8 ,

wherein the sending includes, if the first error bits in the first data read by the first read operation are uncorrectable, sending information including a message indicating whether the life is nearing its end or not to display the message on the display device.

12. The method according to claim 10 , further comprising determining whether or not the number of the first error bits is greater than a threshold, and

wherein the sending includes, if the first error bits is greater than the threshold, sending information about the life of the nonvolatile memory to display the life of the nonvolatile memory on the display device.

13. The method according to claim 8 ,

wherein the nonvolatile semiconductor memory includes a plurality of memory cells, and each of the plurality of memory cells is configured to store two or more than two bits of data.

14. The method according to claim 8 ,

wherein the nonvolatile semiconductor memory is a NAND type flash memory.

Assignments (3)
CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058957/0124 →
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
MERGER Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 058946/0675 →