Addressing scheme for local memory organization
A memory tile, in a local memory, may be considered to be a unit of memory structure that carries multiple memory elements, wherein each memory element is a one-dimensional memory structure. Multiple memory tiles make up a memory segment. By structuring the memory tiles, and a mapping matrix to the memory tiles, within a memory segment, non-blocking, concurrent write and read accesses to the local memory for multiple requestors may be achieved with relatively high throughput. The accesses may be either row-major or column-major for a two-dimensional memory array.
1. A method of memory access, the method comprising:
establishing an addressing scheme for a memory segment, the addressing scheme defining:
a plurality of memory tiles, each memory tile among the plurality of memory tiles designated as belonging to:
a memory bank among a plurality of memory banks; and
a memory sub-bank among a plurality of memory sub-banks;
a plurality of memory entries, each memory entry among the plurality of memory entries extending across the plurality of memory tiles;
each memory tile among the plurality of memory tiles having plurality of memory lines that are associated with a respective memory entry of the plurality of memory entries; and
each memory line among the plurality of memory lines having a plurality of memory elements, wherein each memory element is a one-dimensional memory structure;
selecting, using the addressing scheme, a memory element among the plurality of memory elements in a first memory line among the plurality of memory lines, in a first entry of the plurality of memory entries, of a first memory tile in a first memory bank and a first memory sub-bank, thereby establishing a first selected memory element;
selecting, using the addressing scheme, a memory element among the plurality of memory elements in a second memory line among the plurality of memory lines, in the first entry, of a second memory tile in a second memory bank, thereby establishing a second selected memory element; and
in a single clock cycle:
accessing the first selected memory element as a first memory element f-G-F storing a first matrix element among a plurality of matrix elements, a quantity of matrix elements in the plurality of matrix elements being equivalent to a quantity of memory elements in the plurality of memory elements in each memory line; and
accessing the second selected memory element as a second memory element storing a second matrix element among a second plurality of matrix elements.
2. The method of claim 1 further comprising:
accessing, using the addressing scheme, a memory element, among the plurality of memory elements in a first line of the plurality of memory lines, in the first entry, of a third memory tile, to store a third matrix element; and
accessing, using the addressing scheme, a memory element, among the plurality of memory elements in a second line of the plurality of memory lines in the first entry, of the third memory tile, to store a fourth matrix element.
3. The method of claim 2 wherein:
the third memory tile is designated in the first memory bank; and
the third memory tile is designated in a second memory sub-bank among the plurality of memory sub-banks.
4. The method of claim 3 further comprising, after accessing all memory lines in all memory tiles in the first memory bank:
accessing, using the addressing scheme, a memory element, among the plurality of memory elements in a first line of the plurality of memory lines, in the first entry, of a subsequent memory tile, to store a subsequent matrix element;
accessing, using the addressing scheme, a memory element, among the plurality of memory elements in a second line of the plurality of memory lines in the first entry, of the subsequent memory tile, to store another subsequent matrix element;
the subsequent memory tile is designated in the second memory bank among the plurality of memory banks; and
the subsequent memory tile is designated in the first memory sub-bank.
5. The method of claim 1 , where all accesses are completed within a single memory access clock cycle.
6. An address translation circuit for memory access, the address translation circuit comprising:
a processor adapted to:
establish an addressing scheme for a memory segment, the addressing scheme defining:
a plurality of memory tiles, each memory tile among the plurality of memory tiles designated as belonging to:
a memory bank among a plurality of memory banks; and
a memory sub-bank among a plurality of memory sub-banks;
a plurality of memory entries, each memory entry among the plurality of memory entries extending across the plurality of memory tiles;
each memory tile among the plurality of memory tiles having plurality of memory lines that are associated with a respective memory entry of the plurality of memory entries; and
each memory line among the plurality of memory lines having a plurality of memory elements, wherein each memory element is a one-dimensional memory structure;
select, using the addressing scheme, a memory element among the plurality of memory elements in a first memory line among the plurality of memory lines, in a first entry of the plurality of memory entries, of a first memory tile in a first memory bank and a first memory sub-bank, thereby establishing a first selected memory element;
select, using the addressing scheme, a memory element among the plurality of memory elements in a second memory line among the plurality of memory lines, in the first entry, of a second memory tile in a second memory bank, thereby establishing a second selected memory element; and
in a single clock cycle:
access the first selected memory element as a first memory element storing a first matrix element among a plurality of matrix elements, a quantity of matrix elements in the plurality of matrix elements being equivalent to a quantity of memory elements in the plurality of memory elements in the each memory line; and
access the second selected memory element as a second memory element storing a second matrix element among a second plurality of matrix elements.
7. The address translation circuit of claim 6 wherein the processor is further adapted to:
access, using the addressing scheme, a memory element among the plurality of memory elements in a first line of the plurality of memory lines, in the first entry, of a third memory tile, to store a third matrix element; and
access, using the addressing scheme, a memory element among the plurality of memory elements in a second line of the plurality of memory lines, in the first entry, of the third memory tile, to store a fourth matrix element.
8. The address translation circuit of claim 7 wherein:
the third memory tile is designated in the first memory bank; and
the third memory tile is designated in a second memory sub-bank among the plurality of memory sub-banks.
9. The address translation circuit of claim 8 wherein the processor is further adapted to, after accessing all memory lines in all memory tiles in the first memory bank:
access, using the addressing scheme, a memory element among the plurality of memory elements in a first line of the plurality of memory lines, in the first entry, of a subsequent memory tile, to store a subsequent matrix element;
access, using the addressing scheme, a memory element among the plurality of memory elements in a second line of the plurality of memory lines in the first entry, of the subsequent memory tile, to store another subsequent matrix element;
wherein the subsequent memory tile is designated in the second memory bank among the plurality of memory banks; and
wherein the subsequent memory tile is designated in the first memory sub-bank.
10. The address translation circuit of claim 6 wherein the processor is further adapted to complete all accesses within a single memory access clock cycle.
11. A non-transitory computer-readable medium storing instructions, wherein executing the instructions causes a processor to:
establish an addressing scheme for a memory segment, the addressing scheme defining:
a plurality of memory tiles, each memory tile among the plurality of memory tiles designated as belonging to:
a memory bank among a plurality of memory banks; and
a memory sub-bank among a plurality of memory sub-banks;
a plurality of memory entries, each memory entry among the plurality of memory entries extending across the plurality of memory tiles;
each memory tile among the plurality of memory tiles having plurality of memory lines that are associated with a respective memory entry of the plurality of memory entries; and
each memory line among the plurality of memory lines having a plurality of memory elements, wherein each memory element is a one-dimensional memory structure;
select, using the addressing scheme, a memory element among the plurality of memory elements in a first memory line among the plurality of memory lines, in a first entry of the plurality of memory entries, of a first memory tile in a first memory bank and a first memory sub-bank, thereby establishing a first selected memory element;
select, using the addressing scheme, a memory element among the plurality of memory elements in a second memory line among the plurality of memory lines, in the first entry, of a second memory tile in a second memory bank, thereby establishing a second selected memory element; and
in a single clock cycle:
access the first selected memory element as a first memory element storing a first matrix element among a plurality of matrix elements, a quantity of matrix elements in the plurality of matrix elements being equivalent to a quantity of memory elements in the plurality of memory elements in the each memory line; and
access the second selected memory element as a second memory element storing a second matrix element among a second plurality of matrix elements.