IP Library Granted Patent US 11,394,912
Granted Patent B2
US 11,394,912 · App. 16/999,557 · Granted Jul 19, 2022

Comparator, AD converter, solid-state imaging device, electronic apparatus, and method of controlling comparator

Inventors: Masaki Sakakibara (Kanagawa, JP); Kenichi Aoyagi (Kanagawa, JP); Seiji Yamada (Kanagawa, JP)
Assignee: SONY CORPORATION
H04N5/3745H01L27/1461H01L27/1464H01L27/14612H01L27/14621H01L27/14627H01L27/14634H01L27/14636H01L27/14645H03K5/24H03K5/2481H04N5/378H04N5/379H04N5/37455
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Quick Facts
Patent No.
US 11,394,912
App. No.
16/999,557
Granted
Jul 19, 2022
Kind
B2
Abstract

The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.

Claims (21)

1. An imaging device comprising:

a first semiconductor substrate;

a second semiconductor substrate, wherein the imaging device is formed by stacking the first semiconductor substrate and the second semiconductor substrate;

a pixel circuit including:

a photoelectric converter;

a transfer transistor;

a first differential transistor disposed on the first semiconductor substrate; and

a reset transistor;

a comparator including:

the first differential transistor;

a second differential transistor disposed on the first semiconductor substrate; and

an output node disposed on the second semiconductor substrate; and

a feedback circuit comprising at least one transistor, wherein a gate of a first transistor of the at least one transistor is coupled to the output node.

2. The imaging device according to claim 1 wherein the first transistor is coupled to a power source voltage and a second transistor.

3. The imaging device according to claim 2 , wherein the second transistor is coupled to a ground.

4. The imaging device according to claim 3 , wherein a gate of the first transistor is configured to receive a signal.

5. The imaging device according to claim 1 , wherein the reset transistor is coupled to a gate of the first differential transistor and one of a source and a drain of the first differential transistor.

6. The imaging device according to claim 5 , wherein the second differential transistor is configured to receive a reference signal.

7. The imaging device according to claim 6 , wherein the photoelectric converter converts incident light into a pixel signal.

8. The imaging device according to claim 7 , wherein the first differential transistor is configured to receive a signal based on the pixel signal.

9. The imaging device according to claim 8 , wherein the comparator is configured to compare the signal based on the pixel signal and the reference signal.

Assignments (1)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE APPLICATION NUMBER PREVIOUSLY RECORDED AT REEL: 053563 FRAME: 0103. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 8, 2021
From: SAKAKIBARA, MASAKI; AOYAGI, KENICHI; YAMADA, SEIJI
To: SONY CORPORATION
Reel/Frame 058344/0896 →
Priority Claims (1)
JP 2014-144389 · Jul 14, 2014 · national
Continuity (4)
Continuation 16438219 · Jun 11, 2019
Continuation 15961584 · Apr 24, 2018
Continuation 14916652
Related Publication 20200389615A1 · Dec 10, 2020