IP Library › Granted Patent US 11,417,674
Granted Patent B2
US 11,417,674 · App. 17/000,523 · Granted Aug 16, 2022

Semiconductor memory device and method of manufacturing semiconductor memory device

Inventors: Harumi Seki (Kawasaki, JP); Yuichiro Mitani (Miuragun, JP)
Assignee: Kioxia Corporation
H01L27/1157G11C8/14H01L27/11565H01L27/11578
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Quick Facts
Patent No.
US 11,417,674
App. No.
17/000,523
Granted
Aug 16, 2022
Kind
B2
Abstract

A semiconductor memory device according to an embodiment includes: a semiconductor layer; a gate electrode layer; a first insulating layer provided between the semiconductor layer and the gate electrode layer, the first insulating layer containing silicon (Si), nitrogen (N), and fluorine (F), and the first insulating layer including a first region; a second insulating layer provided between the first insulating layer and the gate electrode layer; and a charge storage layer provided between the first insulating layer and the second insulating layer, the charge storage layer containing silicon (Si) and nitrogen (N), and the charge storage layer including a second region, in which a second atomic ratio (N/Si) in the second region is larger than a first atomic ratio (N/Si) in the first region, and in which a first fluorine concentration in the first region is higher than a second fluorine concentration in the second region.

Claims (29)

1. A semiconductor memory device comprising:

a semiconductor layer;

a gate electrode layer;

a first insulating layer provided between the semiconductor layer and the gate electrode layer, the first insulating layer containing silicon (Si), nitrogen (N), and fluorine (F), and the first insulating layer including a first region;

a second insulating layer provided between the first insulating layer and the gate electrode layer; and

a charge storage layer provided between the first insulating layer and the second insulating layer, the charge storage layer containing silicon (Si) and nitrogen (N), the charge storage layer containing or not containing fluorine (F), and the charge storage layer including a second region,

wherein a second atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the second region is larger than a first atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the first region, and

wherein a first fluorine concentration in the first region is higher than a second fluorine concentration in the second region.

2. The semiconductor memory device according to claim 1 , wherein the first atomic ratio is 1.25 or less.

3. The semiconductor memory device according to claim 1 , wherein the second atomic ratio is more than 1.25.

4. The semiconductor memory device according to claim 1 , wherein the first fluorine concentration is 2×10 20 atoms/cm −3 or more.

5. The semiconductor memory device according to claim 1 , wherein the second fluorine concentration is 1×10 20 atoms/cm 3 or less.

6. The semiconductor memory device according to claim 1 , wherein the first insulating layer contains oxygen (O).

7. The semiconductor memory device according to claim 1 , wherein the first insulating layer contains silicon nitride or silicon oxynitride.

8. The semiconductor memory device according to claim 1 , wherein the charge storage layer contains silicon nitride.

9. The semiconductor memory device according to claim 1 , wherein the semiconductor layer contains fluorine (F).

10. A semiconductor memory device comprising:

a plurality of gate electrode layers disposed in a first direction so as to be spaced apart from each other;

a semiconductor layer extending in the first direction;

a first insulating layer provided between the semiconductor layer and at least one gate electrode layer of the plurality of gate electrode layers, the first insulating layer containing silicon (Si), nitrogen (N), and fluorine (F), and the first insulating layer including a first region;

a second insulating layer provided between the first insulating layer and the at least one gate electrode layer; and

a charge storage layer provided between the first insulating layer and the second insulating layer, the charge storage layer containing silicon (Si) and nitrogen (N), the charge storage layer containing or not containing fluorine (F), and the charge storage layer including a second region,

wherein a second atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the second region is larger than a first atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the first region, and

wherein a first fluorine concentration in the first region is higher than a second fluorine concentration in the second region.

11. The semiconductor memory device according to claim 10 , wherein the first atomic ratio is 1.25 or less.

12. The semiconductor memory device according to claim 10 , wherein the first insulating layer contains silicon nitride or silicon oxynitride.

13. The semiconductor memory device according to claim 10 , wherein the charge storage layer contains silicon nitride.

14. The semiconductor memory device according to claim 10 , further comprising a columnar insulating region extending in the first direction, the columnar insulating region being surrounded by the semiconductor layer, and the columnar insulating region containing fluorine (F).

15. The semiconductor memory device according to claim 10 , wherein the semiconductor layer is surrounded by the plurality of gate electrode layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2022
From: SEKI, HARUMI; MITANI, YUICHIRO
To: KIOXIA CORPORATION
Reel/Frame 058656/0836 →
Priority Claims (1)
JP JP2020-018908 · Feb 6, 2020 · national
Continuity (1)
Related Publication 20210249420A1 · Aug 12, 2021
Cited By (2)
US 12,477,733 US 12,713,639