IP Library › Granted Patent US 11,355,511
Granted Patent B2
US 11,355,511 · App. 17/000,545 · Granted Jun 7, 2022

Semiconductor memory device

Inventors: Tsunehiro Ino (Fujisawa, JP); Akira Takashima (Fuchu, JP); Reika Tanaka (Yokohama, JP)
Assignee: Kioxia Corporation
H01L27/1157H01L27/11565H01L27/11578
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Quick Facts
Patent No.
US 11,355,511
App. No.
17/000,545
Granted
Jun 7, 2022
Kind
B2
Abstract

A semiconductor memory device of an embodiment includes: a semiconductor layer; a gate electrode layer; a first insulating layer provided between the semiconductor layer and the gate electrode layer; a second insulating layer provided between the first insulating layer and the gate electrode layer; and an intermediate layer provided between the first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number 61 ), a space group P4 2 /nmc (space group number 137 ), or a space group R- 3 m (space group number 166 ), and the intermediate layer containing hafnium (Hf), oxygen (O), and nitrogen (N).

Claims (70)

1. A semiconductor memory device comprising:

a semiconductor layer;

a gate electrode layer;

a first insulating layer provided between the semiconductor layer and the gate electrode layer;

a second insulating layer provided between the first insulating layer and the gate electrode layer; and

a charge storage layer provided between the first insulating layer and the second insulating layer, the charge storage layer containing a first crystal of a space group Pbca (space group number 61 ), a space group P4 2 /nmc (space group number 137 ), or a space group R-3m (space group number 166 ), and the charge storage layer containing hafnium (Hf), oxygen (O), and nitrogen (N).

2. The semiconductor memory device according to claim 1 , wherein an atomic ratio of nitrogen (N) to a sum of hafnium (Hf), oxygen (O) and nitrogen (N) contained in the charge storage layer is 1.5% or more and 3.0% or less.

3. The semiconductor memory device according to claim 1 , wherein the charge storage layer contains a second crystal of a space group P2 1 c (space group number 14 ).

4. The semiconductor memory device according to claim 1 , wherein the charge storage layer includes an amorphous region.

5. The semiconductor memory device according to claim 1 , wherein a thickness of the charge storage layer is 2 nm or more and 10 nm or less.

6. The semiconductor memory device according to claim 1 , wherein the first crystal is hafnium oxide.

7. A semiconductor memory device comprising:

a semiconductor layer;

a gate electrode laver;

a first insulating layer provided between the semiconductor layer and the gate electrode layer;

a second insulating layer provided between the first insulating layer and the gate, electrode laver; and

an intermediate layer provided between the first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number 61 ), a space group P4 2 /nmc (space group number 137 ), or a space group R-3m (space group number 166 ), and the intermediate layer containing hafnium (Hf), oxygen (O), and nitrogen (N);

a first silicon nitride layer provided between the first insulating layer and the intermediate layer; and

a second silicon nitride layer provided between the intermediate layer and the second insulating layer.

8. The semiconductor memory device according to claim 7 , wherein a thickness of the first silicon nitride layer is thinner than a thickness of the intermediate layer, and a thickness of the second silicon nitride layer is thinner than the thickness of the intermediate layer.

9. A semiconductor memory device comprising:

a plurality of gate electrode layers spaced apart from each other and arranged in a first direction;

a semiconductor layer extending in the first direction;

a first insulating layer provided between the semiconductor layer and at least one gate electrode layer of the gate electrode layers;

a second insulating layer provided between the first insulating layer and the at least one gate electrode layer; and

a charge storage layer provided between the first insulating layer and the second insulating layer, the charge storage layer containing a first crystal of a space group Pbca (space group number 61 ), a space group P4 2 /nmc (space group number 137 ), or a space group R-3m (space group number 166 ), and the charge storage layer containing hafnium (Hf), oxygen (O), and nitrogen (N).

10. The semiconductor memory device according to claim 9 , wherein an atomic ratio of nitrogen (N) to a sum of hafnium (Hf), oxygen (O) and nitrogen (N) contained in the charge storage layer is 1.5% or more and 3.0% or less.

11. The semiconductor memory device according to claim 9 , wherein the charge storage layer contains a second crystal of a space group P2 1 c (space group number 14 ).

12. The semiconductor memory device according to claim 9 , wherein the charge storage layer includes an amorphous region.

13. The semiconductor memory device according to claim 9 , wherein a thickness of the charge storage layer is 2 nm or more and 10 nm or less.

14. The semiconductor memory device according to claim 9 , wherein the first crystal is hafnium oxide.

15. A semiconductor memory device comprising;

a plurality of gate electrode layers spaced apart from each other and arranged in a first direction;

a semiconductor layer extending in the first direction;

a first insulating layer provided between the semiconductor layer and at least one gate electrode layer of the gate electrode lavers;

a second insulating layer provided between the first insulating layer and the at least one gate electrode layer; and

an intermediate layer provided between first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number 61 ), a space group P4 2 /nmc (space group number 137 ), or a space group R-3m (space group number 166 ), and the intermediate layer containing hafnium (Hf), oxygen (O), and nitrogen (N);

a first silicon nitride layer provided between the first insulating layer and the intermediate layer; and

a second silicon nitride layer provided between the intermediate layer and the second insulating layer.

16. A semiconductor memory device comprising:

a semiconductor layer;

a gate electrode:

a first insulating layer provided between the semiconductor layer and the gate electrode;

a second insulating layer provided between the first insulating layer and the gate electrode; and

an intermediate layer provided between the first insulating layer and the second insulating laver, the intermediate layer containing a first crystal of a space group Pbca (space group number 61 ), a space group P4 2 /nmc (space group number 137 ), or a space group R-3m space group number 166 ), and the intermediate layer containing hafnium (Hf), oxygen (O), and at least one element selected from a group consisting of silicon (Si), germanium (Ge), aluminum (Al), strontium (Sr), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), Yttrium (Y), lanthanoid, and ruthenium (Ru),

wherein an atomic ratio of the at least one element to a sum of hafnium (Hf) and the at least one element contained in the intermediate layer is 6% or more and 15% or less.

17. A semiconductor memory device comprising:

a semiconductor layer;

a gate electrode;

a first insulating layer provided between the semiconductor layer and the grate electrode;

a second insulating layer provided between the first insulating layer and the gate electrode; and

an intermediate layer provided between the first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number 61 ), a space group P4 2 /nmc (space group number 137 ), or a space group R-3m (space group number 166 ), and the intermediate layer containing hafnium (Hf), oxygen and barium (Ba),

wherein an atomic ratio of barium (Ba) to a sum of hafnium (Hf) and barium (Ba) contained in the intermediate layer is 3% or more and 10% or less.

18. A semiconductor memory device comprising:

a semiconductor layer;

a gate electrode;

a first insulating layer provided between the semiconductor layer and the gate electrode;

a second insulating layer provided between the first insulating layer and the Bate electrode; and

an intermediate layer provided between the first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number 61 ), a space group P4 2 /nmc (space group number 137 ), or a space group R-3m (space group number 166 ), and the intermediate layer containing zirconium (Zr) and hafnium (Hf),

wherein an atomic ratio of zirconium (Zr) to a sum of hafnium (Hf) and zirconium (Zr) contained in the intermediate layer is 70% or more.

19. The semiconductor memory device according to claim 7 , wherein an atomic ratio of nitrogen (N) to a sum of hafnium (Hf), oxygen (O) and nitrogen (N) contained in the intermediate layer is 1.5% or more and 3.0% or less.

20. The semiconductor memory device according to claim 7 , wherein the intermediate layer contains a second crystal of a space group P2 1 c (space group number 14 ).

21. The semiconductor memory device according to claim 7 , wherein the intermediate layer includes an amorphous region.

22. The semiconductor memory device according to claim 7 , wherein a thickness of the intermediate layer is 2 nm or more and 10 nm or less.

23. The semiconductor memory device according to claim 7 , wherein the first crystal is hafnium oxide.

24. The semiconductor memory device according to claim 15 , wherein an atomic ratio of nitrogen (N) to a sum of hafnium (Hf), oxygen (O) and nitrogen (N) contained in the intermediate layer is 1.5% or more and 3.0% or less.

25. The semiconductor memory device according to claim 15 , wherein the intermediate layer contains a second crystal of a space group P2 1 c (space group number 14 ).

26. The semiconductor memory device according to claim 15 , wherein the intermediate layer includes an amorphous region.

27. The semiconductor memory device according to claim 15 , wherein a thickness of the intermediate layer is 2 nm or more and 10 nm or less.

28. The semiconductor memory device according to claim 15 , wherein the first crystal is hafnium oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2020
From: INO, TSUNEHIRO; TAKASHIMA, AKIRA; TANAKA, REIKA
To: KIOXIA CORPORATION
Reel/Frame 054608/0516 →
Priority Claims (1)
JP JP2020-049900 · Mar 19, 2020 · national
Continuity (1)
Related Publication 20210296326A1 · Sep 23, 2021