Methods of forming microelectronic devices and memory devices

1. A method of forming a microelectronic device, comprising:

forming a microelectronic device structure, the microelectronic device structure comprising:

a semiconductive base structure;

one or more isolation structures partially vertically extending through the semiconductive base structure;

a memory array region vertically overlying the semiconductive base structure and comprising memory cells; and

a first dielectric material vertically overlying the memory cells;

forming an additional microelectronic device structure separate from the microelectronic device structure, the additional microelectronic device structure comprising a base structure and a second dielectric material vertically overlying the base structure;

bonding the second dielectric material of the additional microelectronic device structure to the first dielectric material of the microelectronic device structure to attach the additional microelectronic device structure to the microelectronic device structure;

removing a portion of the semiconductive base structure down to a surface of at least one of the one or more isolation structures after attaching the additional microelectronic device structure to the microelectronic device structure; and

forming a control logic region vertically over a remaining portion of the semiconductive base structure, the control logic region comprising control logic devices in electrical communication with the memory cells of the memory array region.

2. The method of claim 1 , wherein forming a microelectronic device structure comprises forming the memory array region of the microelectronic device structure to further comprise:

a source tier vertically overlying the semiconductive base structure and comprising at least one source structure;

a stack structure vertically overlying the source tier and comprising a vertically alternating sequence of conductive structures and insulative structures;

cell pillar structures vertically extending through stack structure and in electrical communication with the at least one source structure of the source tier, portions of the cell pillar structures and the conductive structures of the stack structure forming vertically extending strings of the memory cells; and

digit line structures overlying the stack structure and in electrical communication with the vertically extending strings of the memory cells, the first dielectric material vertically overlying the digit line structures.

3. The method of claim 2 , further comprising forming the memory array region of the microelectronic device structure to further comprise conductive contact structures vertically extending through the stack structure.

4. The method of claim 1 , wherein forming a control logic region vertically over a remaining portion of the semiconductive base structure comprises:

forming transistors at least partially vertically overlying the remaining portion of the semiconductive base structure; and

forming conductive routing structures in electrical communication with the transistors, the transistors and the conductive routing structures forming control logic circuitry of the control logic devices of the control logic region.

5. The method of claim 4 , wherein forming conductive routing structures in electrical communication with the transistors comprises forming copper routing structures in electrical communication with the transistors.

6. The method of claim 4 , wherein forming transistors comprises forming each of the transistors to individually comprise:

a source region within the remaining portion of the semiconductive base structure;

a drain region within the remaining portion of the semiconductive base structure;

a channel region within the remaining portion of the semiconductive base structure and horizontally interposed between the source region and the drain region; and

a gate structure vertically overlying and at least partially horizontally overlapping the channel region.

7. The method of claim 6 , further comprising:

forming first conductive contact structures vertically extending between and coupling at least some of the conductive routing structures and at least some of the transistors;

forming second conductive contact structures vertically extending between and coupling pairs of the conductive routing structures; and

forming third conductive contact structures vertically extending from one or more of conductive routing structures, through the remaining portion of the semiconductive base structure, and to at least one conductive structure vertically overlying and in electrical communication with the memory cells of the memory array region.

8. The method of claim 1 , further comprising:

forming conductive routing structures over and in electrical communication with the control logic devices of the control logic region; and

forming conductive pad structures over and in electrical communication with the conductive routing structures.

9. The method of claim 8 , wherein:

forming conductive routing structures comprises forming the conductive routing structures to comprise copper; and

forming conductive pad structures comprises forming the conductive pad structures to comprise aluminum.

10. A method of forming a memory device, comprising:

forming a first memory device structure, the first memory device structure comprising:

a semiconductive base structure;

one or more isolation structures partially vertically extending through the semiconductive base structure; and

a source structure over the semiconductive base structure;

a stack structure over the source structure, the stack structure comprising tiers each comprising a conductive structure and an insulative structure vertically neighboring the conductive structure;

digit line structures over the stack structure;

strings of memory cells vertically extending through stack structure and in electrical communication with the source structure and the digit line structures; and

a first dielectric structure over the digit line structures;

forming a second memory device structure, the second memory device structure comprising a base structure and a second dielectric structure over the base structure;

bonding the first dielectric structure of the first memory device structure to the second dielectric structure of the second memory device structure;

removing a portion of the semiconductive base structure down to a surface of at least one of the one or more isolation structures after bonding the first dielectric structure of the first memory device structure to the second dielectric structure of the second memory device structure; and

forming control logic circuitry over and in electrical communication with the source structure after bonding the first dielectric structure of the first memory device structure to the second dielectric structure of the second memory device structure.

11. The method of claim 10 , wherein bonding the first dielectric structure of the first memory device structure to the second dielectric structure of the second memory device structure comprises:

vertically inverting the first memory device structure;

providing the vertically inverted first memory device structure over the second memory device structure; and

bonding the first dielectric structure of the vertically inverted first memory device structure to the second dielectric structure of the second memory device structure to form a connected dielectric structure.

12. The method of claim 10 , wherein forming control logic circuitry over and in electrical communication with the source structure:

forming transistors at least partially overlying a remaining portion of the semiconductive base after removing the portion of the semiconductive base structure down to the surface of the at least one of the one or more isolation structures; and

forming conductive routing structures vertically over the transistors, the conductive routing structures coupled to the transistors by way of first conductive contact structures, and the conductive routing structures coupled the source structure by way of at least one second conductive contact structure vertically extending through the at least one of the one or more isolation structures.

13. The method of claim 10 , wherein forming control logic circuitry over and in electrical communication with the source structure comprises forming CMOS circuitry over and in electrical communication with the source structure.