Memory device having 2-transistor vertical memory cell and shared channel region
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.
1. An apparatus comprising:
a first data line located in a first level of the apparatus;
a second data line located in a second level of the apparatus;
a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and
a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.
2. The apparatus of claim 1 , wherein the first and second transistors have different transistor types, and the third and fourth transistors have different transistor types.
3. The apparatus of claim 1 , wherein the first and second transistors have different threshold voltages, and the third and fourth transistors have different threshold voltages.
4. The apparatus of claim 1 , wherein each of the first and second charge storage structures includes polysilicon.
5. The apparatus of claim 1 , wherein:
the second transistor includes a first semiconducting oxide material contacting the first data line and the first charge storage structure; and
the fourth transistor includes a second semiconducting oxide material contacting the second data line and the second charge storage structure.
6. The apparatus of claim 1 , further comprising:
a first conductive line spanning across part of each of the first and second transistors; and
a second conductive line spanning across part of each of the third and fourth transistors.
7. The apparatus of claim 6 , further comprising:
a first additional conductive line spanning across part of each of the first and second transistors; and
a second additional conductive line spanning across part of each of the third and fourth transistors.
8. The apparatus of claim 1 , further comprising:
a third data line located in the first level;
a fourth data line located in the second level;
a third memory cell located in the third level, the third memory cell including a fifth transistor coupled to the third data line, and a sixth transistor coupled to the fifth transistor;
a fourth memory cell located in the fourth level, the fourth memory cell including a seventh transistor coupled to the fourth data line, and an eighth transistor coupled to the seventh transistor, the seventh transistor coupled in series with the fifth transistor between the third and fourth data lines;
a first conductive line spanning across part of each of the first and second transistors, and part of each of the fifth and sixth transistors; and
a second conductive line spanning across part of each of the third and fourth transistors, and part of each of the seventh and eighth transistors.
9. The apparatus of claim 8 , further comprising:
a first additional conductive line spanning across part of each of the first and second transistors, and part of each of the fifth and sixth transistors; and
a second additional conductive line spanning across part of each of the third and fourth transistors, and part of each of the seventh and eighth transistors.
10. An apparatus comprising:
a first conductive region located in a first level of the apparatus;
a second conductive region located in a second level of the apparatus;
a first charge storage structure located in a third level of the apparatus between the first and second levels;
a first semiconductor material located between and contacting the first conductive region and the first charge storage structure;
a second charge storage structure located in a fourth level of the apparatus between the second and third levels;
a second semiconductor material located between and contacting the second conductive region and the second charge storage structure;
a third semiconductor material extending between the first and second levels and contacting the first and second conductive regions;
a first dielectric located between and contacting the first and second charge storage structures; and
a second dielectric separating the third semiconductor material from each of the first and second semiconductor materials and the first and second charge storage structures.
11. The apparatus of claim 10 , further comprising a fourth semiconductor material extending between the first and second levels and contacting the first and second conductive regions.
12. The apparatus of claim 11 , further comprising a third dielectric separating the fourth semiconductor material from each of the first and second semiconductor materials and the first and second charge storage structures.
13. The apparatus of claim 10 , wherein:
the first charge storage structure forms part of a first transistor of a first memory cell;
the second charge storage structure forms part of a second transistor of a second memory cell; and
the third semiconductor material forms a shared channel region of the first and second transistors.
14. The apparatus of claim 10 , wherein each of the first and second semiconductor materials has a first conductivity type, and the third semiconductor material has a second conductivity type.
15. The apparatus of claim 10 , wherein each of the first and second semiconductor materials has an n-type conductivity, and the third semiconductor material has a p-type conductivity.
16. The apparatus of claim 10 , wherein the first semiconductor material comprises a same material as the second semiconducting material.
17. The apparatus of claim 10 , wherein each of the first and second semiconductor materials comprises a semiconducting oxide material.
18. The apparatus of claim 10 , wherein each of the first and second semiconductor materials comprises at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In 2 O 3 ), tin oxide (SnO 2 ), titanium oxide (TiOx), zinc oxide nitride (Zn x O y N z ), magnesium zinc oxide (MgZn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).
19. The apparatus of claim 10 , further comprising:
a third conductive region spanning across part of each of the first and third semiconductor materials; and
a fourth conductive region spanning across part of each of the second and third semiconductor materials.
20. The apparatus of claim 19 , further comprising:
a third additional conductive region spanning across part of each of the first and third semiconductor materials;
a fourth additional conductive region spanning across part of each of the second and third semiconductor materials.