Apparatus and methods for power amplifier distortion network
Apparatus and methods for power amplifier distortion networks are disclosed. In one aspect, there is provided a power amplifier system including a power amplifier configured to amplify a radio frequency input signal. The power amplifier including an input configured to receive the radio frequency input signal and an output configured to generate an amplified radio frequency signal. The power amplifier system further includes a distortion network electrically coupled to either the input or the output of the power amplifier. The distortion network including a plurality of channelized resistors. The channelized resistors connected in series to either an input or an output of the power amplifier.
1. A power amplifier system comprising:
a power amplifier configured to amplify a radio frequency input signal, the power amplifier including an input configured to receive the radio frequency input signal and an output configured to generate an amplified radio frequency signal; and
a distortion network electrically coupled to either the input or the output of the power amplifier, the distortion network including a plurality of channelized resistors, the channelized resistors connected in series to either an input or an output of the power amplifier, each of the channelized resistors formed as a transistor without a gate or a transistor having a floating gate.
2. The power amplifier system of claim 1 wherein the input of the power amplifier includes a pair of differential inputs, the output of the power amplifier includes a pair of differential outputs, and the distortion network is connected between either the differential inputs or the differential outputs.
3. The power amplifier system of claim 1 wherein the distortion network is connected between ground and one of the input and the output of the power amplifier.
4. The power amplifier system of claim 1 wherein a channel width of each of the channelized resistors is selected to reduce gain compression of the power amplifier.
5. The power amplifier system of claim 1 wherein a channel length of each of the channelized resistors is selected to reduce gain compression of the power amplifier.
6. The power amplifier system of claim 1 wherein the distortion network further includes a capacitor connected in series with the plurality of channelized resistors.
7. The power amplifier system of claim 6 wherein a capacitance of the channelized resistor is selected to reduce phase compression of the power amplifier.
8. The power amplifier system of claim 1 wherein distortion network is formed on a same die as the power amplifier.
9. The power amplifier system of claim 1 wherein, for each of the channelized resistors, the conductivity of the channelized resistor is dependent only on a drain-to-source voltage applied to the channelized resistor.
10. The power amplifier system of claim 1 wherein the transistor of each of the channelized resistors includes a field-effect transistor not including the gate electrode or a field-effect transistor having the floating gate electrode.
11. A power amplifier die comprising:
a power amplifier configured to amplify a radio frequency input signal, the power amplifier including an input configured to receive the radio frequency input signal and an output configured to generate an amplified radio frequency signal; and
a distortion network electrically coupled to either the input or the output of the power amplifier, the distortion network including a plurality of channelized resistors, the channelized resistors connected in series to either an input or an output of the power amplifier, each of the power amplifier and the distortion network formed on the power amplifier die, each of the channelized resistors formed as a transistor without a gate or a transistor having a floating gate.
12. The power amplifier die of claim 11 wherein the input of the power amplifier includes a pair of differential inputs, the output of the power amplifier includes a pair of differential outputs, and the distortion network is connected between either the differential inputs or the differential outputs.
13. The power amplifier die of claim 11 wherein the distortion network is connected between ground and one of the input and the output of the power amplifier.
14. The power amplifier die of claim 11 wherein a channel width of each of the channelized resistors is selected to reduce gain compression of the power amplifier.
15. The power amplifier die of claim 11 wherein the distortion network further includes a capacitor connected in series with the plurality of channelized resistors.
16. The power amplifier die of claim 15 wherein a capacitance of the channelized resistor is selected to reduce phase compression of the power amplifier.
17. A mobile device comprising:
an antenna;
a power amplifier configured to amplify a radio frequency input signal, the power amplifier including an input configured to receive the radio frequency input signal and an output configured to generate an amplified radio frequency signal, the power amplifier further configured to provide the amplified radio frequency signal to the antenna; and
a distortion network electrically coupled to either the input or the output of the power amplifier, the distortion network including a plurality of channelized resistors, the channelized resistors connected in series to either an input or an output of the power amplifier, each of the power amplifier and the distortion network formed on the power amplifier die, each of the channelized resistors formed as a transistor without a gate or a transistor having a floating gate.
18. The mobile device of claim 17 wherein the input of the power amplifier includes a pair of differential inputs, the output of the power amplifier includes a pair of differential outputs, and the distortion network is connected between either the differential inputs or the differential outputs.
19. The mobile device of claim 17 wherein the distortion network is connected between ground and one of the input and the output of the power amplifier.