Physically obfuscated circuit

1. A physically obfuscated circuit comprising:

a plurality of subcircuits, each subcircuit comprising

at least one p-channel field effect transistor;

at least one n-channel field effect transistor;

a first power supply terminal configured to receive a first supply voltage with an upper supply potential; and

a second power supply terminal configured to receive a second supply voltage with a lower supply potential;

wherein the at least one p-channel field effect transistor and the at least one n-channel field effect transistor are connected such that

the at least one n-channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p-channel field effect transistor; and

the at least one p-channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel field effect transistor; and

a precharge circuit configured to precharge the subcircuit to a first state in which the potential at the gate of the at least one n-channel field effect transistor is lower than the upper supply potential and the potential at the gate of the at least one p-channel field effect transistor is higher than the lower supply potential; and

wherein the physically obfuscated circuit further comprises a physically obfuscated circuit value bit generation circuit configured to generate at least one physically obfuscated circuit value bit depending on which of the subcircuits first enters a second state in which the potential at the gate of the at least one n-channel field effect transistor is the upper supply potential and the potential at the gate of the at least one p-channel field effect transistor is the lower supply potential.

2. Physically obfuscated circuit according to claim 1 , wherein the precharge circuit is configured to let the subcircuits start transitioning from the first state to the second state after precharging the subcircuits to the first state.

3. Physically obfuscated circuit according to claim 2 , wherein the precharge circuit is configured to let the subcircuits start transitioning from the first state to the second state by means of supplying a common input signal to the subcircuits.

4. Physically obfuscated circuit according to claim 1 , wherein the precharge circuit is configured to precharge the circuit to the first state in response to the reception of a request for a physically obfuscated circuit value.

5. Physically obfuscated circuit according to claim 1 , wherein the second state is a steady state of the subcircuit and the first state is an inverse state of the second state.

6. Physically obfuscated circuit according to claim 1 , wherein in the first state the potential at the gate of the at least one n-channel field effect transistor is the lower supply potential and the potential at the gate of the at least one p-channel field effect transistor is the higher supply potential.

7. Physically obfuscated circuit according to claim 1 , wherein in the first state the potential at the gate of the at least one n-channel field effect transistor is a potential to turn off the n-channel field effect transistor and the potential at the gate of the at least one p-channel field effect transistor is a potential to turn off the p-channel field effect transistor.

8. Physically obfuscated circuit according to claim 1 , wherein the physically obfuscated circuit value bit generation circuit is configured to receive, from each subcircuit, a signal indicating the state of the subcircuit.

9. Physically obfuscated circuit according to claim 8 , wherein the physically obfuscated circuit value bit generation circuit comprises a latch circuit supplied with the signal indicating the state of the subcircuit from each subcircuit and configured to be switched in a stable state depending on which of the subcircuits first enters the second state.

10. Physically obfuscated circuit according to claim 1 , wherein the plurality of subcircuits comprises three or more subcircuits and the physically obfuscated circuit value bit generation circuit is configured to generate a plurality of physically obfuscated circuit value bits depending on an order in which the subcircuits enter the second state.

11. Physically obfuscated circuit according to claim 1 , wherein each subcircuit comprises:

a plurality of p-channel field effect transistors;

wherein the p-channel field effect transistors and the at least one n-channel field effect transistor are connected such that

the at least one n-channel field effect transistor, if supplied with a upper supply potential at its gate, supplies the lower supply potential to the gates of the p-channel field effect transistors; and

the p-channel field effect transistors, if supplied with the lower supply potential at their gates, supply the upper supply potential to the gate of the at last one n-channel field effect transistor.

12. Physically obfuscated circuit according to claim 1 , wherein each subcircuit comprises:

a plurality of n-channel field effect transistors;

wherein the n-channel field effect transistors and the at least one p-channel field effect transistor are connected such that

the at least one p-channel field effect transistor, if supplied with a lower supply potential at its gate, supplies the higher supply potential to the gates of the n-channel field effect transistors; and

the n-channel field effect transistors, if supplied with the higher supply potential at their gates, supply the lower supply potential to the gate of the at last one p-channel field effect transistor.

13. Physically obfuscated circuit according to claim 1 , wherein each subcircuit comprises:

a plurality of p-channel field effect transistors;

a plurality of n-channel field effect transistors;

wherein the p-channel field effect transistors and the n-channel field effect transistors are connected such that

the n-channel field effect transistors, if supplied with a upper supply potential at their gates, supply the lower supply potential to the gates of the p-channel field effect transistors; and

the p-channel field effect transistors, if supplied with the lower supply potential at their gates, supply the upper supply potential to the gates of the n-channel field effect transistors.

14. Physically obfuscated circuit according to claim 13 , wherein the p-channel field effect transistors are connected in series and their gates are connected and the n-channel field effect transistors are connected in series and their gates are connected.

15. Physically obfuscated circuit according to claim 1 , further comprising a key generator configured to generate a cryptographic key based on the physically obfuscated circuit value bit.

16. Physically obfuscated circuit according to claim 1 , wherein in the first state the potential at the gate of the at least one n-channel field effect transistor depends on a field effect transistor threshold voltage of a field effect transistor of the precharge circuit.

17. Physically obfuscated circuit according to claim 1 , wherein in the first state the potential at the gate of the at least one p-channel field effect transistor depends on a field effect transistor threshold voltage of a field effect transistor of the precharge circuit.

18. Physically obfuscated circuit according to claim 1 , wherein in the first state the potential at the gate of the at least one n-channel field effect transistor is the lower supply potential plus a field effect transistor threshold voltage of a field effect transistor of the precharge circuit.

19. Physically obfuscated circuit according to claim 1 , wherein in the first state the potential at the gate of the at least one p-channel field effect transistor is the higher supply potential minus a field effect transistor threshold voltage of a field effect transistor of the precharge circuit.